Flash Memory Programming Sequence Reducing Disturb
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Solution Overview
Problem
Multi-level cell flash memory devices face inaccuracies and charge loss due to programming procedures and retention issues, leading to random distortions in measured charge levels, which affect the reliability and accuracy of stored data.
Innovation Solution
A method of programming nonvolatile memory blocks in phases of decreasing bit significance, where each phase programs all pages with the same bit significance, reducing programming disturbs by applying different pass voltages and sequencing the programming of MSB, CSB, and LSB pages to minimize interference between adjacent cells, and optimizing the erase process to reduce wear and reliability failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-level cell flash memory devices store more than one bit per cell by applying multiple charge levels, then storage capacity increases, but measurement precision deteriorates due to random distortion from programming inaccuracies and charge loss
Solution Approach 1:
The patent segments the programming process into multiple phases (e.g., SLC programming phase followed by MLC programming phase) and divides charge level adjustment into incremental steps. Each phase programs specific bit significance (MSB, CSB, LSB) separately, allowing precise control of charge levels while maintaining measurement accuracy despite increased storage capacity
Solution Approach 2:
The patent applies preliminary programming actions by first programming cells to intermediate charge levels (SLC mode with fewer bits per cell) before final programming to target MLC levels. This preliminary SLC programming establishes a foundation that reduces subsequent programming disturbs and improves measurement precision during the transition to multi-bit storage
2Manufacturing precision
If programming is performed in multiple stages with incremental charge level adjustments, then manufacturing precision improves, but programming time increases
Solution Approach 1:
The patent implements periodic programming actions by alternating between programming phases and read-verify phases. The process cycles through programming incrementally (e.g., programming MSB, then CSB, then LSB) with periodic verification reads to ensure charge levels are within target ranges, achieving high manufacturing precision without excessive time loss through efficient phase transitions
Solution Approach 2:
Preliminary SLC programming is performed before final MLC programming, establishing intermediate charge levels that reduce the magnitude of subsequent programming adjustments. This preliminary action decreases the number of incremental steps needed, thereby reducing total programming time while maintaining precision
3Productivity
If pass voltage is applied to idle rows during programming to maintain device operation, then productivity is maintained, but harmful factors increase due to programming disturbs in adjacent cells
Solution Approach 1:
The patent applies different pass voltage levels to different rows based on their programming status. Active rows receiving programming have one voltage level, while idle rows receive different or reduced pass voltage levels. This local differentiation minimizes programming disturbs to adjacent cells while maintaining productivity through continued operation of non-programmed rows
Solution Approach 2:
The pass voltage applied to idle rows is dynamically adjusted based on the current programming phase and adjacent cell states. During phases where adjacent cells are being programmed, pass voltage to idle rows is reduced or modified to minimize disturbs, while being restored when adjacent programming is complete, thereby balancing productivity and harm reduction dynamically
4Device complexity
If conventional programming sequences are used without optimized sequencing, then device complexity remains low, but reliability deteriorates due to increased wear from unoptimized erase processes
Solution Approach 1:
The erase process is segmented into multiple phases corresponding to the programming phases (SLC erase phase, MLC erase phase). Each erase phase is optimized for its specific programming context, with different voltage sequences and timing parameters. This segmented approach improves reliability by reducing cumulative wear without requiring complex overall device architecture
Solution Approach 2:
Preliminary erase actions are performed before programming phases to ensure cells start from a known clean state. The erase process is optimized to remove only necessary charge without excessive stress on cells, and preliminary verification ensures complete erasure before proceeding to programming, thereby extending device lifespan through reduced wear
Data Source
AI summary
A method, device and computer readable medium for programming a nonvolatile memory block. The method may include programming information, by a memory controller, to the nonvolatile memory block by performing a sequence of programming phases of descending bit significances. The device may include a nonvolatile memory block; and a memory controller that may be configured to determine a bit significance level of the nonvolatile memory block; program the nonvolatile memory block by performing at least one programming phase; and program the nonvolatile memory block to an erase value that may be higher than the pre-erase value; wherein the erase value and the pre-erase value may be selected based on the bit significance level of the nonvolatile memory block. The method may include packing three single level cell (SLC) nonvolatile memory blocks to one three-bit per cell nonvolatile memory block in order of the three SLC bit significances.