Word Line Zone Biasing for Single-Side GIDL Erase Control
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Solution Overview
Problem
Non-volatile memory arrays face challenges in efficiently performing single-side gate-induced drain leakage (GIDL) erase operations without disturbing unselected sub-blocks, particularly due to varying erase disturb and threshold voltage margin loss across different sub-blocks, exacerbated by word lines with differing diameters.
Innovation Solution
Applying distinct unselect bias voltages to different word line zones based on memory hole diameter to ensure selective erasure of a sub-block while minimizing disturbance to unselected sub-blocks during GIDL erase operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single unselect bias voltage is applied to all word lines during GIDL erase operation, then the erase operation can be performed, but erase disturb occurs in unselected sub-blocks and threshold voltage margin is lost
Solution Approach 1:
The patent applies different unselect bias voltages to different word line zones based on their specific characteristics (memory hole diameter). Word lines with larger diameters receive one bias voltage while those with smaller diameters receive another, optimizing the erase operation for each local region while preventing erase disturb in unselected sub-blocks.
Solution Approach 2:
The patent changes the unselect bias voltage parameter from a single uniform value to multiple differentiated values assigned to different word line zones. This parameter differentiation allows the system to achieve both efficient erasure in selected sub-blocks and protection of unselected sub-blocks from erase disturb.
2Reliability
If higher unselect bias voltage is applied to all word lines to prevent erase disturb, then data integrity in unselected sub-blocks is maintained, but erase efficiency in selected sub-blocks decreases
Solution Approach 1:
The patent tailors the unselect bias voltage to the local characteristics of each word line zone. Word lines with larger diameters (which are more prone to erase disturb) receive higher bias voltages, while word lines with smaller diameters receive lower bias voltages, achieving both data integrity and erase efficiency without compromising either.
Solution Approach 2:
The patent segments the word line set into multiple zones based on memory hole diameter characteristics. Each zone is assigned a specific unselect bias voltage, allowing differentiated control that optimizes both erase efficiency and data integrity for each segment simultaneously.
3Device complexity
If uniform word line bias is applied during GIDL erase, then device complexity is minimized, but manufacturing precision of erase operation deteriorates due to varying word line diameters
Solution Approach 1:
The patent implements local quality control by assigning different unselect bias voltages to different word line zones based on their diameter characteristics. This approach achieves precise erase control for each word line zone while maintaining manageable device complexity through systematic voltage assignment.
Solution Approach 2:
The patent segments word lines into zones with similar diameter characteristics and applies unified bias voltages to each zone. This segmentation approach balances precision requirements with control complexity by grouping word lines that respond similarly to the same bias voltage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances the efficiency and accuracy of single-side GIDL erase operations by reducing erase disturb and maintaining threshold voltage margins, thereby minimizing uncorrectable errors and improving data integrity.
Implementation Method 1
perform a single-side gate-induced drain leakage (GIDL) erase operation on the memory block
Data Source
AI summary
Embodiments disclosed herein are directed to performing a single-side gate-induced drain leakage (GIDL) erase operation. Control circuitry may be configured to perform a single-side GIDL erase operation on a memory block in which a selected sub-block is erased while an unselected sub-block is not erased. During the single-side GIDL erase operation, the control circuitry may be configured to apply a first unselect bias voltage to a first set of word lines of the unselected sub-block, where the first set of word lines is associated with a first word line zone and the first word line zone is associated with an unselect bias voltage, and apply a second unselect bias voltage to a second set of word lines of the unselected sub-block, where the second set of word lines is associated with a second word line zone and the second word line zone is associated with another unselect bias voltage.