Semiconductor Memory Cell Layout for NAND-DRAM Speed Retention

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Existing semiconductor memory devices face challenges in integrating non-volatile NAND flash memory and volatile DRAM technologies to achieve high-speed data storage and retrieval while maintaining efficient data retention and capacity.

Innovation Solution

A semiconductor memory device is designed with a configuration that combines NAND flash memory for non-volatile data storage and DRAM for volatile data storage, utilizing a first bit line connected to a first memory cell transistor and a first capacitor, with a novel layout and circuit design that enhances data storage capacity and retention.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Duration of action of stationary object

If NAND flash memory is used for non-volatile data storage, then data retention capability is improved, but data access speed deteriorates

Engineering Contradiction:

Improvedata retention capabilityVSAvoiddata access speed

Core Design Contradiction:

Duration of action of stationary objectVSSpeed

Solution Approach 1:

The patent combines NAND flash memory cells and DRAM memory cells into a single memory device, allowing the system to leverage both non-volatile data retention and high-speed data access capabilities within one integrated structure

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The memory device performs multiple functions by incorporating both NAND flash memory for non-volatile storage and DRAM memory for volatile high-speed storage, enabling the single device to handle diverse data storage requirements with different performance characteristics

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Speed

If DRAM is used for volatile data storage, then data access speed is improved, but data retention capability deteriorates

Engineering Contradiction:

Improvedata access speedVSAvoiddata retention capability

Core Design Contradiction:

SpeedVSDuration of action of stationary object

Solution Approach 1:

The patent integrates DRAM memory cells with NAND flash memory cells in one device, allowing fast data access through DRAM while maintaining data retention through NAND flash

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The memory device provides multi-functional storage capabilities by incorporating both DRAM for high-speed volatile storage and NAND flash for non-volatile data retention, serving multiple data storage needs simultaneously

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Reliability

If separate NAND flash and DRAM devices are used, then data retention and speed requirements are met, but device complexity and integration increase

Engineering Contradiction:

Improvedata retention and speed performanceVSAvoidintegration complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges NAND flash memory cells and DRAM memory cells into a single integrated memory device, reducing system complexity by eliminating the need for separate memory devices while maintaining both data retention and high-speed access capabilities

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The integrated memory device provides universal storage functionality by incorporating both NAND flash and DRAM memory types, allowing a single device to replace multiple separate memory devices and simplify system architecture

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS12575115B2Semiconductor memory device

Publication Date: 2026.03.10 KIOXIA CORP

AI summary

According to one embodiment, a semiconductor memory device includes: a first bit line; a first memory cell transistor coupled to the first bit line; and a first capacitor coupled between the first memory cell transistor and the first bit line.