Dynamic Erase Depth for Non-Volatile Memory Endurance
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Solution Overview
Problem
Non-volatile memory devices, such as NAND flash memory, experience endurance degradation due to charge trapping in insulating or dielectric layers during erase and program cycles, leading to reduced performance as the number of cycles increases, especially as memory cells scale down in size.
Innovation Solution
The solution involves dynamically adjusting the erase depth based on the upper tail of the erase distribution after programming, by adjusting the erase verify level or the number of erase pulses, to improve endurance by ensuring that memory cells remain in the intended erased state and maintain optimal threshold voltage levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory cells are deeply erased to ensure they remain in the erased state, then reliability of the erased state is improved, but endurance deteriorates due to increased charge trapping in dielectric layers
Solution Approach 1:
The patent applies dynamics by making the erase verify level adjustable rather than fixed. The erase verify level is dynamically adapted based on the number of erase/program cycles the memory has undergone. For memory with fewer cycles, a higher (deeper) erase verify level is used to ensure thorough erasing. For memory with more cycles, a lower (shallower) erase verify level is used to reduce stress on degraded dielectric layers, thereby extending endurance while maintaining adequate erased state reliability.
2Duration of action of stationary object
If memory cells are shallowly erased to improve endurance, then endurance is improved, but reliability of the erased state deteriorates due to increased errors
Solution Approach 1:
The patent resolves this contradiction by dynamically adjusting the erase verify level based on the memory's cycle history. Instead of using a fixed shallow erase verify level that would compromise reliability, the system adapts the verify level to match the current condition of the memory cells. This ensures that erased state reliability is maintained at appropriate levels while still applying reduced stress to extend endurance.
3Reliability
If the erase verify level is increased to deepen the erase, then erased state reliability is improved, but stress on dielectric layers increases causing more charge trapping
Solution Approach 1:
The patent applies dynamics by making the erase verify level adaptive rather than static. The system adjusts the erase verify level based on the number of erase/program cycles the memory has experienced. For memory with fewer cycles, a higher erase verify level is applied to ensure deep erasing and high reliability. For memory with more cycles, a lower erase verify level is used to minimize additional stress and charge trapping on already degraded dielectric layers, thereby reducing harmful effects while maintaining adequate reliability.
4Object-generated harmful factors
If the erase verify level is decreased to reduce stress on dielectric layers, then charge trapping is reduced, but erased state reliability deteriorates
Solution Approach 1:
The patent resolves this contradiction by dynamically adjusting the erase verify level based on the memory's cycle history. Instead of using a fixed low erase verify level that would compromise reliability, the system adapts the verify level to match the current condition. This ensures that charge trapping is minimized while still maintaining adequate erased state reliability through appropriate verification thresholds.
Data Source
AI summary
Improving endurance for non-volatile memory by dynamic erase depth is disclosed. A group of memory cells are erased. Then, at least some of the erased memory cells are programmed. Programming the memory cells typically impacts the erase threshold distribution of those memory cells that were intended to stay erased. The erase depth of the next erase can be adjusted based on how the program operation affects the erase threshold distribution. As one example, the upper tail of the erase distribution is measured after programming. The higher the upper tail, the shallower the next erase, in one embodiment. This helps to improve endurance. In one embodiment, the erase depth is adjusted by determining a suitable erase verify level. Rather than (or in addition to) adjusting the erase verify level, the number of erase pulses that are performed after erase verify passes can be adjusted to adjust the erase depth.