Semiconductor Memory Select Transistor Wear Distribution
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Solution Overview
Problem
Semiconductor memory devices experience reliability deterioration due to repeated erase operations, as existing technologies do not effectively manage the wear and tear on select transistors during erase cycles.
Innovation Solution
A semiconductor memory device with a memory cell array and a peripheral circuit unit that includes an erase count storage unit and control logic, which determines the select transistors to apply erase operation voltage based on the erase count value, selectively using different transistor groups to generate a gate-induced drain leakage current and distribute the deterioration across multiple transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If erase operations are repeatedly performed on memory blocks, then data storage capacity is maintained, but reliability of select transistors deteriorates due to accumulated wear and tear
Solution Approach 1:
The memory block is divided into multiple sub-blocks, and the select transistor group is divided into multiple sub-groups (first through fourth sub-groups). By segmenting the erase operations across different sub-blocks and alternating between different sub-groups of select transistors, the wear is distributed rather than concentrated on a single group, thereby improving overall reliability while maintaining erase cycle capability
Solution Approach 2:
Different select transistor sub-groups are selectively activated based on the erase count value and sub-block being erased. The control logic applies erase operation voltages to specific sub-groups (e.g., first and second sub-groups for even erase counts, third and fourth sub-groups for odd erase counts) depending on the local requirements of each sub-block, thereby optimizing the distribution of stress and improving transistor reliability
2Reliability
If erase operation voltage is applied to all select transistors, then complete erase operation is achieved, but deterioration of select transistors accelerates
Solution Approach 1:
The select transistor group is segmented into multiple sub-groups that can be independently controlled. During erase operations, only the necessary sub-groups are activated based on which sub-blocks require erasing, rather than applying voltage to all select transistors. This reduces cumulative stress on individual transistor groups while maintaining complete erase functionality across all memory blocks
Solution Approach 2:
The control logic implements periodic alternation between different select transistor sub-groups based on erase count values. For example, even erase counts activate the first and second sub-groups while odd erase counts activate the third and fourth sub-groups. This periodic switching distributes the operational burden across multiple transistor groups, improving durability without compromising erase efficiency
3Reliability
If multiple select transistor groups are used to distribute wear, then reliability improves, but device complexity increases
Solution Approach 1:
The memory block is segmented into sub-blocks with dedicated select transistor sub-groups for each. This segmentation allows the control logic to manage complexity by handling smaller, more manageable units rather than controlling all transistors uniformly. The erase count storage unit tracks wear per sub-block, enabling targeted management that improves reliability while keeping control logic organized and manageable
Solution Approach 2:
The erase count storage unit provides feedback about the wear state of each memory block to the control logic. Based on this feedback, the control logic dynamically selects which select transistor sub-groups to activate for subsequent erase operations. This feedback mechanism enables intelligent load distribution that improves reliability without requiring overly complex control logic, as the decisions are based on simple count comparisons
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents reliability deterioration by dispersing the deterioration of select transistors, thereby improving the operational reliability of the semiconductor memory device during repeated erase operations.
Implementation Method 1
determine at least one select transistor to which an erase operation voltage is to be applied based on an erase count value that is the number of erase operations performed on the cell string. While a pre-erase voltage is applied to a source line of the selected cell string, the erase operation voltage may be applied to the determined at least one select transistor
Data Source
AI summary
There may be provided a semiconductor memory device including a memory cell array, an erase count storage unit, and a control logic. The memory cell array may include a plurality of memory blocks. Each of the plurality of memory blocks may include a plurality of cell strings. The erase count storage unit may be configured to store an erase count value for each of the plurality of memory blocks. During an erase operation of a memory block, the erase operation may be performed based on the erase count value.