eFuse Memory Fuse Pairing for Fail-to-Write-1 Reliability

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Solution Overview

Problem

Efuse memories face programming failures due to fail-to-write-1 issues, particularly under advanced processes, leading to reliability concerns and increased area requirements in existing redundant backup methods.

Innovation Solution

Incorporating a backup fuse and backup selection control transistor in parallel with the main fuse and selection control transistor, allowing independent programming and series connection during read operations, ensuring the series resistance exceeds a threshold for effective programming even if the main fuse fails.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If two-position redundant backup mode is used to increase programming reliability, then programming reliability is improved, but area increases by 100%

Engineering Contradiction:
Improveprogramming reliabilityVSAvoidmemory area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The efuse unit is segmented into a main fuse and a backup fuse, each with independent selection control transistors. This segmentation allows the backup fuse to be activated only when the main fuse programming fails, providing reliability improvement without requiring complete redundancy of the entire efuse unit, thus reducing area overhead compared to traditional two-position redundant backup mode.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The backup fuse is prepared in advance with a larger cross-sectional area to ensure it can be successfully programmed even under advanced process conditions. The backup fuse remains idle during normal operation and is activated only when programming failure of the main fuse is detected, allowing preliminary preparation of a more robust backup element without continuous area occupation.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If fuse cross-sectional area is increased to ensure programming success, then programming reliability is improved, but area consumption increases

Engineering Contradiction:
Improveprogramming success rateVSAvoidfuse area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

Different parts of the efuse structure have different cross-sectional areas optimized for their specific functions: the main fuse has a smaller cross-sectional area for normal operation, while the backup fuse has a larger cross-sectional area specifically optimized for reliable programming. This local differentiation allows the backup fuse to achieve higher programming success rate without increasing the area of the main fuse or other parts of the system.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design enhances programming reliability by minimizing area increase and avoiding programming failures, maintaining effective programming states without affecting normal programming efficiency.

Implementation Method 1

the backup fuse is subjected to electromigration to increase a resistance value of the backup fuse to obtain a backup programming resistance value

Methodology Applied
Scientific EffectElectromigration:

Data Source

PatentUS20260066036A1Efuse memory and operation method thereof
Publication Date: 2026.03.05 SHANGHAI HUALI INTEGRATED CIRCUIT CORP
  • US20260066036A1 patent drawing
  • US20260066036A1 patent drawing
  • US20260066036A1 patent drawing

AI summary

The present application discloses an efuse memory, and an efuse unit includes: a main fuse, a backup fuse, a main selection control transistor, and a backup selection control transistor. A first end of the main fuse and a first end of the backup fuse are connected. The main selection control transistor is connected between a second end of the main fuse and a source port. The backup selection control transistor is connected between a second end of the backup fuse and the source port. The second end of the backup fuse serves as a read port. In a programming operation, the main fuse and the backup fuse form a parallel structure. In a read operation, the backup fuse and the main fuse form a series structure. The present application also discloses a method for operating an efuse memory.