Memory Device Progressive Row Reading Latency Reduction
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Solution Overview
Problem
Current memory devices experience significant initial latency due to propagation delays in pre-charging memory cells, particularly in stand-alone devices with a large number of cells, which limits their scalability and access time.
Innovation Solution
The proposed solution involves grouping memory cells into sets and using a dummy structure and synchronization circuit to pre-charge data items in the first portion of a row without waiting for all cells to be pre-charged, reducing initial latency by enabling early data retrieval from the first portion of the row.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all memory cells in a row are pre-charged before reading, then data accuracy is ensured, but initial latency increases significantly
Solution Approach 1:
The patent divides a row of memory cells into multiple segments (first portion and second portion). The first portion can be read before the entire row is pre-charged, while the second portion waits for complete pre-charging. This segmentation allows partial data retrieval to reduce latency while maintaining data accuracy for critical portions.
Solution Approach 2:
The patent performs preliminary pre-charging of the first portion of memory cells in a row before the entire row is fully pre-charged. This preliminary action enables early reading of the first portion, reducing initial latency. The system monitors pre-charge completion and selectively enables reading based on which portions are ready.
2Quantity of substance
If the number of memory cells per row is increased to improve capacity, then storage density improves, but propagation delays increase
Solution Approach 1:
By segmenting long rows into multiple portions, the patent reduces the effective pre-charge distance for each segment. The first portion can be pre-charged and read faster than waiting for the entire long row, thus maintaining speed while supporting higher overall capacity through increased row length.
Solution Approach 2:
The patent dynamically adjusts the reading strategy based on pre-charge status. Different portions of the row can be read at different times based on when they become ready, rather than waiting for a fixed global pre-charge completion signal. This dynamic approach optimizes access speed for varying row lengths and capacities.
3Reliability
If the entire row is pre-charged before reading, then data integrity is maintained, but access time increases
Solution Approach 1:
The patent segments the row into portions with different integrity requirements. The first portion can be read with acceptable integrity before full pre-charge completion, while the second portion waits for complete pre-charging. This selective segmentation maintains data integrity for critical data while improving overall access time.
Solution Approach 2:
The patent changes the pre-charge parameter (voltage level or timing) for different portions of the row. The first portion may use reduced pre-charge timing or voltage thresholds that allow earlier reading, while the second portion uses full pre-charge parameters. This parameter differentiation maintains data integrity where needed while optimizing access time.
Data Source
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AI summary
A memory device including: a memory array (2) with a plurality of memory cells (3) arranged in rows and columns and a plurality of word lines (WL) and bit lines (BL); a dummy structure (30) including a dummy row (38) of dummy cells and a dummy word line (WLD); a first pre-charging stage (5), which biases a word line of the memory array; an output stage (4, 10, 34, 35) including a plurality of sense amplifiers (SA1, SA2, SA3), each sense amplifier generating a corresponding output signal representing a datum stored in a corresponding memory cell pre-charged by the first pre-charging stage; and a second pre-charging stage (32, 36), which biases the dummy word line simultaneously with the word line biased by the first pre-charging stage. The output stage includes an enable stage (34), which detects a state of complete pre-charging of at least one intermediate dummy cell. A first part of the sense amplifiers (SA1, SA2) generate the corresponding output signals following upon sensing of the state of complete pre-charging of the intermediate dummy cell.