Nonvolatile Memory Page Buffer Latch Sets for Read Voltage Optimization
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Solution Overview
Problem
Nonvolatile semiconductor memory devices face challenges in reducing error bits and improving data reliability during read operations, particularly in determining the data state of memory cells due to variations in threshold voltage distributions.
Innovation Solution
The nonvolatile memory device employs a page buffer with multiple latch sets and a control logic that performs multiple read operations using different read voltages to count memory cells with specific threshold voltages, selecting optimal data based on cell counts and voltage levels to enhance data reliability and read performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple read operations are performed with different read voltages to determine data state, then data reliability is improved, but device complexity increases
Solution Approach 1:
The page buffer is divided into multiple latch sets (first latch set, second latch set, third latch set) that can independently store data from different read operations. This segmentation allows simultaneous or sequential storage of multiple read results without interfering with each other, enabling reliable data state determination through multiple readings while maintaining buffer organization.
Solution Approach 2:
The patent introduces a temporal dimension by performing read operations at different develop periods (first develop period, second develop period, third develop period). Data from readings at different time points are stored in different latch sets, allowing the system to analyze threshold voltage distributions across multiple time points to determine the most reliable data state.
2Measurement precision
If multiple latch sets are used to store read operation results, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The control logic compares data stored in different latch sets to determine the final data state. This feedback mechanism uses the results from multiple read operations stored in separate latch sets to verify and refine the determination of memory cell states, improving measurement precision through iterative comparison and validation.
3Reliability
If sequential read operations are performed at different develop periods, then data reliability is improved, but read time increases
Solution Approach 1:
The patent performs read operations continuously at different develop periods without idle intervals. The first, second, and third read operations are executed in sequence with each subsequent operation building on the previous ones, maintaining continuous useful action to minimize total read time while still gathering multiple data samples for reliable determination.
Data Source
AI summary
Disclosed is a nonvolatile memory device. The nonvolatile memory device includes a cell array including a plurality of memory cells, a page buffer including a plurality of latch sets, and a control logic. The page buffer is connected to the cell array through bit lines. The latch sets respectively are configured to sense data from selected memory cells among the memory cells through the bit lines. The latch sets respectively are configured to perform a plurality of read operations to determine one data state. The latch sets are respectively configured to store results of the read operations. The control logic configured to control the page buffer such that the latch sets sequentially and respectively store the results of the read operations, to compare data stored in the latch sets with each other, and to select one latch set among the latch sets based on the comparison result.