Memory Page Refresh During Write Operations to Limit Disturbs
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Solution Overview
Problem
High-density memory circuits face data integrity issues due to programming or erase disturbs in non-selected storage transistors, which are vulnerable to interference from capacitive coupling during write operations.
Innovation Solution
A method is employed to divide memory pages into refresh groups, concurrently performing write operations and writing back read data, while limiting disturbs by applying reduced voltage differences and using a partial refresh scheme to ensure data integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If high-density memory circuits are used to increase storage capacity, then the quantity of data storage is improved, but programming or erase disturbs in non-selected storage transistors increase due to capacitive coupling
Solution Approach 1:
The memory array is divided into multiple independently controllable blocks, each with its own word lines and bit lines. During write operations, only the selected block experiences full voltage swings, while other blocks are isolated with reduced voltage differences, preventing disturbs from propagating across the entire high-density array.
Solution Approach 2:
Different voltage conditions are applied to different regions of the memory array simultaneously. The selected block receives full programming/erase voltages while non-selected blocks maintain reduced voltage differences, creating localized zones of different electrical characteristics that prevent capacitive coupling disturbs while maintaining high-density storage.
2Reliability
If voltage difference is increased to ensure reliable programming or erasing of selected storage transistors, then the reliability of write operations is improved, but disturbs to non-selected storage transistors increase due to capacitive coupling
Solution Approach 1:
The patent applies full voltage differences locally only to the selected word line and bit line intersections, while non-selected lines maintain reduced voltage differences. This localized voltage application ensures reliable programming/erasing at the target location without propagating harmful capacitive coupling effects across the entire memory array.
Solution Approach 2:
The memory array is segmented into independently controlled blocks, allowing full voltage swings to be confined to the selected block during write operations. This segmentation isolates the high-voltage stress to only where needed, ensuring write reliability while preventing disturbs in other blocks.
3Reliability
If refresh operations are performed frequently to maintain data integrity, then data integrity is improved, but the productivity of write operations decreases due to additional operation overhead
Solution Approach 1:
The patent performs refresh operations on non-selected blocks in advance, before they are needed for write operations. By proactively refreshing data in blocks that will be accessed soon, the system ensures data integrity is maintained without causing delays to critical write path operations, thus preserving productivity.
Solution Approach 2:
Refresh operations are performed periodically on non-selected blocks during idle periods or between write operations, rather than continuously interfering with the write path. This periodic refreshing maintains data integrity while minimizing impact on write operation throughput by utilizing otherwise idle time windows.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces program and erase disturbs, maintaining data integrity by ensuring that storage transistors do not deviate from their programmed or erased states, even under high-density conditions.
Implementation Method 1
non-selected transistors must be protected from inadvertently being set into the programmed or the erased state during a programming or erase operation, as they are vulnerable to interference or 'disturb' arising from the bias voltages (e.g., by capacitive coupling)
Data Source
AI summary
A method for writing data into storage transistors in a memory array where the storage transistors are organized into multiple memory pages with the storage transistors in the memory pages being associated with a respective word line. The method includes, in response to a first memory page being selected for write operation, selecting a second memory page from the multiple memory pages; reading data from the second memory page; and concurrently (i) performing the write operation on the first memory page, and (ii) writing the data read from the second memory page back into the second memory page.