Vertical Nonvolatile Memory Contact Structure for Higher Read-Erase Current
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Solution Overview
Problem
Existing nonvolatile memory devices face challenges in increasing data storage capacity and improving the operation characteristics of three-dimensionally arranged vertical memory cells.
Innovation Solution
The vertical nonvolatile memory device incorporates a specific structure with vertical channel structures, first and second gate lines, semiconductor lines, and contact plugs, including semiconductor and metal contact plugs, to enhance read and erase operations by optimizing electron and hole paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertical nonvolatile memory devices with three-dimensionally arranged vertical memory cells are used to increase data storage capacity, then storage capacity increases, but operation characteristics deteriorate
Solution Approach 1:
The patent segments the memory device into distinct functional regions: a first region with vertical channel structures and word lines for data storage, and a second region with different doping types for current enhancement. This segmentation allows optimization of each region's function to resolve the contradiction between high capacity and good operation characteristics.
Solution Approach 2:
The patent applies local quality by doping only specific regions (source and drain regions in the second region) with impurities of a second conductivity type, while maintaining undoped or differently doped regions in the first region. This localized doping enhances read and erase currents without compromising the overall memory cell structure and data storage functionality.
2Ease of manufacture
If conventional memory cell structures are used, then manufacturing is simpler, but read and erase currents are insufficient
Solution Approach 1:
The patent embeds a second region within or adjacent to the first region, creating a nested structure where the source and drain regions of the second region are positioned to enhance the electrical characteristics of the vertical channel structures. This nesting approach maintains structural compactness while significantly improving read and erase currents through the localized doping enhancement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves the operation characteristics of three-dimensionally arranged vertical memory cells by increasing read and erase currents, thereby enhancing the performance of the memory device.
Implementation Method 1
a plurality of semiconductor contact plugs of a second conductivity type, the plurality of semiconductor contact plugs being connected to the plurality of vertical channel structures by passing through the first semiconductor line and the second gate line
Implementation Method 2
the first semiconductor line including a first ohmic contact region; the second semiconductor line including a second ohmic contact region
Data Source
AI summary
A vertical nonvolatile memory device includes vertical channel structures, first gate lines extending in a horizontal direction while surrounding the vertical channel structures and apart from each other in a vertical direction, a second gate line extending in the horizontal direction on the first gate lines, a first semiconductor line of a first conductivity type and extending in the horizontal direction on the second gate line, semiconductor contact plugs of a second conductivity type and connected to the vertical channel structures by passing through the first semiconductor line and the second gate line, a second semiconductor line of a second conductivity type extending in the horizontal direction on the semiconductor contact plugs and connected to the semiconductor contact plugs, a first metal contact plug connected to the first semiconductor line, and a second metal contact plug connected to the second semiconductor line.