Non-Volatile Memory Erase Pulses With Adjustable Kick Voltage

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Solution Overview

Problem

Existing non-volatile memory systems experience reduced erase efficiencies when relying on Gate Induced Drain Leakage (GIDL) for erasing memory cells, leading to potential errors in data programming.

Innovation Solution

Implementing an adjustable erase voltage with a kick voltage and adjusted time duration based on memory conditions to enhance erase efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If Gate Induced Drain Leakage (GIDL) is used for erasing memory cells, then the erase process can be implemented, but erase efficiency is reduced leading to potential programming errors

Engineering Contradiction:

Improveprogramming accuracyVSAvoiderase efficiency

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent applies parameter changes by dynamically adjusting the erase voltage magnitude and pulse duration based on memory block conditions. The controller monitors erase progress and modifies voltage parameters (applying higher voltage for longer duration when needed) to achieve complete erasure, thereby resolving the contradiction between erase efficiency and programming accuracy.

Inventive Principle:

Principle #35Parameter changes

2Productivity

If a fixed erase voltage is applied to memory cells, then the erase process is simple to implement, but erase efficiency is reduced when memory blocks require multiple erase cycles

Engineering Contradiction:

Improveerase efficiencyVSAvoiderase control complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent implements dynamics by transitioning from a fixed erase voltage to a dynamic, adjustable erase voltage system. The controller adapts voltage magnitude and pulse duration based on real-time monitoring of erase status, enabling efficient single-pass erasure while managing complexity through intelligent control algorithms.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent applies feedback by monitoring the erase process status and using this information to adjust subsequent erase voltage parameters. The controller detects whether memory blocks are properly erased and modifies voltage application accordingly, creating a closed-loop system that improves erase efficiency while maintaining manageable complexity through adaptive control.

Inventive Principle:

Principle #23Feedback

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Improves erase efficiency and reduces errors in non-volatile memory systems by optimizing the erase process.

Implementation Method 1

Existing non-volatile memory systems experience reduced erase efficiencies when relying on Gate Induced Drain Leakage (GIDL) for erasing memory cells

Methodology Applied

Scientific EffectGate Induced Drain Leakage (GIDL):

Data Source

PatentUS20260065999A1Non-volatile memory with adjustable erase voltage

Publication Date: 2026.03.05 SANDISK TECHNOLOGIES LLC

AI summary

An adjustable kick voltage and an adjustable time duration are adjusted/set based on one or more conditions of a non-volatile memory. During an erase process, an erase voltage pulse is applied to a set of non-volatile memory cells of the non-volatile memory including driving an erase pulse voltage magnitude to an elevated voltage that is equal to a base erase voltage plus the adjusted kick voltage for the adjusted time duration and then reducing the erase pulse voltage magnitude to the base erase voltage for the remainder of the erase voltage pulse