Active-Area eFuse Cell Layout for Smaller Memory Arrays
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Solution Overview
Problem
The existing efuse cell layout, which typically includes a MOS transistor and a link in a metal layer, occupies a large area, limiting the overall efuse memory area efficiency.
Innovation Solution
The efuse cell structure is redesigned with the link structure positioned in an active area layer, parallel to the MOS transistor, allowing for a combined layout that reduces the cell dimensions and array area by integrating the link structure into the active area, forming a centrally symmetric efuse cell pair.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the link structure is positioned in a metal layer separate from the MOS transistor, then the electrical connection and programming function are achieved, but the efuse cell area becomes large
Solution Approach 1:
The patent merges the link structure with the MOS transistor active area by positioning the link within the same active area layer. The link is formed using the same active area material (e.g., doped semiconductor region) as the MOS transistor, eliminating the need for separate metal layer routing and reducing overall cell area while maintaining electrical connectivity functionality.
Solution Approach 2:
The patent transitions the link structure from a traditional planar metal layer layout to a vertical integration within the active area layer. By using the active area material itself to form the link (through selective doping or material deposition), the design exploits the third dimension (vertical layering within the active area) to reduce lateral footprint and improve area efficiency.
2Area of stationary object
If the MOS transistor area is reduced to decrease cell size, then the overall efuse area decreases, but the reliability and programming function may be compromised
Solution Approach 1:
The patent combines the link structure with the MOS transistor active area, where the link is formed using the same doped semiconductor region that serves as the transistor's active area. This merging allows the link to be programmed through electromigration or defect formation in the shared active area material, maintaining programming reliability while reducing the need for separate dedicated link structures.
Solution Approach 2:
The active area material serves multiple functions: it forms the conductive channel for the MOS transistor operation and simultaneously forms the link structure for efuse programming. This multi-functionality eliminates redundant structures and reduces cell area while preserving both transistor control functionality and efuse programming reliability through the shared active area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This redesign significantly reduces the efuse cell area by 11% compared to conventional designs, improving layout area utilization and efficiency.
Implementation Method 1
When the efuse cell structure is in an initial state, the active area link is in the on state, and the drain and the bit line are electrically connected together
Implementation Method 2
It achieves an on-chip programming function with high reliability by fusing the link based on the principle of electromigration (EM)
Data Source
AI summary
The present disclosure provides an efuse memory, where an efuse cell structure includes a control transistor composed of a MOS transistor and a link structure. The MOS transistor is formed in a first active area. The link structure is formed in a second active area parallel to the first active area. The link structure includes first and second link connection areas, and an active area link located between the first and second link connection areas. The first link connection area is connected to a drain line of the MOS transistor. The second link connection area is connected to a bit line. The active area link includes on and off states.