NAND Flash Memory Bitline Segmentation for Floating Gate Coupling
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Solution Overview
Problem
Conventional NAND flash memory architectures face significant challenges due to increasing parasitic capacitance coupling between adjacent floating gates, leading to incorrect threshold voltage readings and programming issues as memory sizes decrease.
Innovation Solution
The proposed solution involves rearranging bitlines in the memory array such that all even bitlines are grouped together and all odd bitlines are grouped separately, allowing simultaneous programming of adjacent cells on the same word line, with optional use of non-connected dummy bitlines and increased isolation to reduce floating gate coupling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory size is decreased to increase density, then memory density is improved, but parasitic capacitance coupling between adjacent floating gates increases
Solution Approach 1:
The memory array is divided into even and odd bitline groups that are physically separated and programmed independently. This segmentation allows adjacent cells on the same word line to be programmed simultaneously without capacitive coupling interference, as cells on even bitlines and odd bitlines are programmed in separate operations.
Solution Approach 2:
The patent introduces a new dimension to the programming operation by enabling simultaneous programming of adjacent cells on the same word line through separate even/odd bitline groups. This adds a temporal dimension to what was previously a sequential process, effectively utilizing the third dimension (time) to resolve the spatial coupling problem.
2Ease of manufacture
If conventional NAND architecture is used with adjacent even and odd rows, then manufacturing simplicity is maintained, but floating gate coupling affects verification and reading operations
Solution Approach 1:
The memory array is segmented into even and odd bitline groups that are physically separated and programmed independently. This segmentation allows adjacent cells on the same word line to be programmed simultaneously without capacitive coupling interference, as cells on even bitlines and odd bitlines are programmed in separate operations.
Solution Approach 2:
The patent introduces dummy bitlines as intermediary elements between functional bitlines. These dummy bitlines act as buffers that further reduce capacitive coupling effects during programming operations, improving the reliability of verification and reading operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly reduces bitline to bitline floating gate coupling, enabling simultaneous programming of adjacent cells while maintaining the same number of cells per word line, thereby improving the accuracy of data verification and reduction in floating gate interference.
Implementation Method 1
parasitic capacitance coupling between adjacent memory cell floating gates becomes a problem
Data Source
AI summary
A NAND memory architecture arranges all even bitlines of a page together, and arranges all odd bitlines of a page together, so that programming operations are carried out on adjacent bitlines on the same word line to reduce floating gate coupling. Non-connected bitlines can be used at boundaries between even and odd sections of the array to further reduce floating gate coupling.