Hierarchical Bit Line Switching for Memory Access Speed
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Solution Overview
Problem
In large semiconductor memory devices, the hierarchical bit line structure leads to increased parasitic resistance and capacitance in switch control lines, causing timing skew between local and global bit lines, which decreases access speed and increases chip size due to the need for more complex circuitry and larger layouts.
Innovation Solution
A semiconductor device with a hierarchical bit line structure that includes global and local bit lines, hierarchical switches, and switch drivers, where the local switch drivers and main switch drivers are configured in a small scale to control the connection state of hierarchical switches efficiently, preventing timing skew and reducing chip area by aligning drivers in the X decoder region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the memory cell array becomes large in size, then capacity increases, but parasitic resistance and capacitance of switch control lines increase causing timing skew and decreased access speed
Solution Approach 1:
The patent divides the large memory cell array into multiple blocks, each with its own local hierarchical switches and control lines. This segmentation allows each block to be controlled independently with shorter control lines, reducing parasitic effects and timing skew while maintaining large overall capacity through the combination of multiple blocks.
2Area of stationary object
If the number of hierarchical switches increases, then memory cell array coverage improves, but switch control line load increases causing timing skew
Solution Approach 1:
The control system is segmented into local switch drivers that control individual hierarchical switches within each block. Each local switch driver manages only the switches in its vicinity, dividing the overall control complexity into manageable segments and reducing the load on any single control line.
Solution Approach 2:
Local switch drivers act as intermediary components between the main word drivers and the hierarchical switches. These intermediaries buffer and distribute control signals locally, reducing the direct load on main control lines and enabling better timing control across the entire memory array.
3Adaptability or versatility
If hierarchical word line structure is employed, then memory cell accessibility improves, but circuit scales of sub-word drivers and main word drivers increase
Solution Approach 1:
The word line driving function is segmented into sub-word drivers that handle individual sub-word lines and main word drivers that handle main word lines. This segmentation allows each driver to be optimized for its specific function and reduces the complexity of any single driver circuit while maintaining comprehensive memory cell accessibility.
Data Source
AI summary
Disclosed herein is a semiconductor device comprising local bit lines, a global bit line, local switch control lines, main switch control lines, hierarchical switches controlling electrical connections between the local bit lines and the global bit line in response to potentials of the local switch control lines, local switch drivers driving the local switch control lines in response to potentials of the main switch control lines, and main switch drivers selectively activating the main switch control lines.