Page Buffer Testing for Unconnected Nonvolatile Memory Cells

The patent introduces an intermediary testing mechanism by creating a virtual discharging path that simulates the presence of memory cells. This intermediary structure allows the page buffer circuit to be tested without actual memory cell connections, thereby maintaining manufacturing efficiency while restoring test coverage. The intermediary path uses discharge transistors and conduction lines to mimic the electrical behavior of connected memory cells during testing.

The patent creates a copy of the memory cell's electrical characteristics by forming a discharging path that replicates the on-state behavior of memory cells. This copying approach allows the testing system to evaluate the page buffer circuit as if memory cells were connected, without requiring actual physical connections. The copy is achieved through discharge transistors configured to simulate memory cell discharge characteristics.

The patent segments the testing function from the main memory operation by creating a dedicated discharging path that is separate from the normal memory cell connection. This segmentation allows the testing mechanism to be activated independently during manufacturing tests without affecting the core memory structure. The discharge transistors and conduction lines form a distinct testing subsystem that can be controlled separately from memory operations.

The patent implements partial action by providing a discharging path that mimics only the essential on-state characteristics of memory cells needed for testing the page buffer circuit. Rather than creating a complete replica of memory cell functionality, the solution focuses on reproducing the specific electrical behavior required for buffer testing, thereby minimizing the added complexity while achieving sufficient test coverage.