FEFET Programming Pulses for Disturb Mitigation in NAND Memory
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Solution Overview
Problem
NAND devices with ferroelectric field-effect transistors (FEFETs) face reliability challenges due to disturb issues.
Innovation Solution
A memory device with ferroelectric transistors that includes a semiconductor layer, a gate electrode, an interfacial layer, and a ferroelectric layer, where a mitigation pulse with opposite polarity to the program pulse is applied to reduce disturb, followed by a program pulse without delay, and a disturb mitigation scheme is employed to periodically restore threshold voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a program pulse is applied to program a desired program state in the ferroelectric transistor, then the memory device achieves data storage functionality, but disturb occurs in the ferroelectric transistor
Solution Approach 1:
A mitigation pulse with opposite polarity to the program pulse is applied to the gate electrode before the program pulse to detrap electrons and prevent disturb. This preliminary counter-action offsets the harmful effect that would otherwise occur during programming, allowing the program pulse to successfully program the desired state without causing disturb.
Solution Approach 2:
The mitigation pulse utilizes the same ferroelectric layer and gate structure that causes disturb when improperly controlled. By applying a controlled pulse of opposite polarity, the system converts the potential harmful effect (electron trapping causing disturb) into a beneficial effect (electron detrapping to prevent disturb), turning the vulnerable component into a protective mechanism.
2Reliability
If a mitigation pulse with opposite polarity is applied to detrap electrons, then disturb is reduced, but additional operation complexity is introduced
Solution Approach 1:
The mitigation pulse and program pulse are merged into a single sequential operation sequence. The mitigation pulse is applied first to detrap electrons, followed immediately by the program pulse to program the desired state. This combining of two functions into one operation sequence reduces overall system complexity while achieving both disturb reduction and data programming.
Solution Approach 2:
The mitigation pulse is applied periodically or in sequence with the program pulse rather than continuously. This periodic application allows the system to maintain simplicity by applying the counter-action only when needed (before programming operations), rather than requiring continuous complex monitoring and adjustment throughout all operations.
3Productivity
If the program pulse is applied immediately after the mitigation pulse without delay time, then operation speed is improved, but control precision requirements increase
Solution Approach 1:
The mitigation pulse is applied as a preliminary action before the program pulse, preparing the ferroelectric layer by detrapping electrons. This preliminary preparation ensures that when the program pulse is applied immediately afterward, the system is already in the optimal state for programming, reducing the need for delay times while maintaining control precision.
Solution Approach 2:
The mitigation pulse and program pulse are applied in continuous sequence without interruption or delay. This continuous application of useful actions (first detrapping, then programming) maximizes operation speed by eliminating idle time, while the integrated control mechanism ensures timing precision is maintained throughout the seamless transition between pulses.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces disturb in FEFETs by detrap electrons and restores threshold voltages, enhancing the reliability and performance of the memory device.
Implementation Method 1
A level of the mitigation pulse may be sufficient to detrap electrons in the ferroelectric transistor
Implementation Method 2
A level of the program pulse may correspond to a level of a write voltage sufficient to program a desired program state in the ferroelectric transistor
Data Source
AI summary
A memory device may include processing circuitry connected to a ferroelectric transistor through a word line and a bit line. The ferroelectric transistor may include an interfacial layer between a gate electrode and a semiconductor layer, and a ferroelectric layer between the interfacial layer and the gate electrode. The processing circuitry may be configured to perform an operation to reduce disturb in the ferroelectric transistor by applying a mitigation pulse to the gate electrode of the ferroelectric transistor using the word line and then applying a program pulse to the gate electrode of the ferroelectric transistor using the word line. The mitigation pulse and the program pulse may have opposite polarities. A level of the program pulse may be sufficient to program a desired program state in the ferroelectric transistor. A level of the mitigation pulse may be sufficient to detrap electrons in the ferroelectric transistor.