Semiconductor Memory Signal Controller for Redundancy Management
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Solution Overview
Problem
Semiconductor memory devices face yield improvements due to defective memory cells, which existing technologies address by replacing defective cells with redundancy cells, but there is a need for efficient management of wordlines to enable and block these cells effectively.
Innovation Solution
A semiconductor memory device design that includes two memory blocks and a signal controller, which generate and manage blocking and enable signals for wordlines, enabling redundancy wordlines to replace defective ones, ensuring proper operation by enabling or disabling wordlines based on defect detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If redundancy wordlines are shared between memory blocks to improve yield, then defective memory cells can be replaced effectively, but the complexity of managing blocking and enable signals across multiple memory blocks increases
Solution Approach 1:
The patent merges the blocking signal management for multiple memory blocks by having the first memory block's blocking signal (first blocking signal) also control the second memory block's wordlines through sharing the same blocking signal line. This consolidation reduces the number of independent blocking signals needed while maintaining the ability to replace defective cells across both memory blocks, thereby improving yield without proportionally increasing signal management complexity
Solution Approach 2:
The patent introduces a signal controller as an intermediary component that coordinates the blocking and enable signals between the first and second memory blocks. This mediator manages the interactions between redundancy wordlines and regular wordlines across blocks, simplifying the overall signal management architecture while enabling effective defect replacement across shared redundancy resources
2Ease of operation
If blocking signals are generated independently for each memory block, then each block can be controlled separately, but the overall device complexity and signal routing increase
Solution Approach 1:
The patent combines blocking signal generation by having the first memory block generate both the first blocking signal (for its own wordlines) and the second blocking signal (shared with the second memory block). This merging approach allows independent control capability while reducing signal routing complexity, as one memory block serves as the primary controller for both blocking signals, simplifying the overall signal distribution architecture
Data Source
AI summary
A semiconductor memory device includes a first memory block, a second memory block, and a signal controller. The first memory block is configured to generate a first blocking signal, a second blocking signal, and a first enable signal in response to a row address, and to block and enable wordlines of the memory block in response to the first blocking signal and the first enable signal, respectively. The second memory block is configured to generate a third blocking signal, a fourth blocking signal, and a second enable signal in response to the row address, and to block and enable wordlines of the second memory block in response to the third blocking signal and the second enable signal, respectively. The signal controller is connected between the first memory block and the second memory block and is configured to enable the third blocking signal when the second blocking signal is enabled, and to enable the first blocking signal when the fourth blocking signal is enabled.