Selective Erase Schemes for Memory Reliability Risks
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Solution Overview
Problem
Existing memory device erase schemes face challenges in balancing data retention and power consumption, with normal erase schemes offering quick and low-power operations but poor data retention, while alternative erase schemes improve data retention but at the cost of higher power consumption and longer erase times.
Innovation Solution
Implementing a selective erase scheme that uses a normal erase scheme for non-reliability-risk memory portions to reduce power consumption and erase time, while employing an alternative erase scheme with two erase pulses or a single pulse with voltage toggling for reliability-risk portions to enhance data retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a normal erase scheme is used, then power consumption and erase time are reduced, but data retention deteriorates
Solution Approach 1:
The patent applies different erase voltage patterns to different subsets of word lines based on their reliability risk profiles. High-risk word lines receive enhanced erase voltages applied to both even and odd subsets, while low-risk word lines receive standard erase voltages only on odd subsets, optimizing the balance between data retention and power consumption locally rather than uniformly across all word lines
Solution Approach 2:
The patent divides word lines into multiple subsets (even and odd subsets) and applies different erase schemes to each subset. This segmentation allows the system to selectively apply higher power erase operations only to specific word line subsets that require improved data retention, rather than increasing power consumption for all word lines
2Reliability
If an alternative erase scheme is used, then data retention is improved, but power consumption and erase time increase
Solution Approach 1:
The patent segments the erase operation into multiple phases targeting different word line subsets. By dividing word lines into even and odd subsets and applying erase operations sequentially to each subset rather than simultaneously to all word lines, the system improves data retention for high-risk lines while avoiding the need to extend erase time proportionally to the entire memory array
Solution Approach 2:
The patent applies enhanced alternative erase schemes only to specific word line subsets identified as high-risk, while using standard erase schemes for low-risk subsets. This localized application of enhanced erase operations improves data retention where needed without uniformly increasing erase time across the entire memory device
3Reliability
If an alternative erase scheme is used, then data retention is improved, but power consumption increases
Solution Approach 1:
The patent implements local quality by applying different erase voltage magnitudes to different word line subsets based on their reliability risk. High-risk word lines receive higher erase voltages to improve data retention, while low-risk word lines receive standard erase voltages, thereby improving overall data retention without proportionally increasing total power consumption
Solution Approach 2:
The patent segments the memory array into multiple word line subsets and applies differentiated erase power levels to each segment. This allows the system to concentrate power consumption on specific high-risk subsets that require enhanced data retention, rather than uniformly increasing power consumption across all word lines
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach achieves improved data retention for reliability-risk memory areas while minimizing power consumption and erase time, offering a tradeoff between data integrity and operational efficiency.
Implementation Method 1
applying a greater voltage (e.g., several volts) to other portions of the block of memory (e.g., a bit line, a select gate drain (SGD), a select gate source (SGS), or the like) in order to cause tunneling of electrons stored in the various memory cells
Data Source
AI summary
In some implementations, a memory device may receive, from a host device, an erase command associated with erasing host data from a portion of a memory. The memory device may determine that the portion of the memory is associated with a reliability risk. The memory device may perform, based on determining that the portion of the memory is associated with the reliability risk, an alternative erase scheme to erase the host data from the portion of the memory, wherein during a first portion of the alternative erase scheme, a first voltage is applied to even word lines and a second voltage, that is different from the first voltage, is applied to odd word lines, and wherein during a second portion of the alternative erase scheme, a third voltage is applied to the even word lines and a fourth voltage is applied to the odd word lines.