Flash Memory Bias Circuit with Dummy Decoding Path
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Solution Overview
Problem
Existing bias circuits for non-volatile memory cells, particularly flash memories, face limitations in accurately biasing drain terminals, leading to deterioration and systematic errors due to unstable current contributions and temperature variations, affecting the stability and accuracy of program and erase operations.
Innovation Solution
A circuit comprising a reference current generator, bias resistive divider, voltage regulator, dummy decoding path, and compensation stage, which generates a stable reference current and cell bias voltage, and injects a compensation current to balance the bias current, reducing dependence on temperature and process spread, thereby ensuring accurate biasing of flash memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a reference current generator is used to simulate cell current during programming, then the biasing stability is improved, but temperature variations and process spread affect other current contributions that add to the reference current, causing biasing inaccuracies
Solution Approach 1:
The patent uses a dummy decoding path that replicates the actual decoding path of the memory array. This dummy path copies the transistor stack configuration and current flow characteristics, allowing accurate simulation of the voltage drops and current contributions without being affected by temperature and process variations in the actual memory cells. The dummy path serves as a reference model that accurately reflects the electrical characteristics of the real array.
Solution Approach 2:
The patent introduces a compensation current as an intermediary element that actively counterbalances the unwanted current contributions from temperature and process variations. The compensation current is generated to match the variations in the dummy decoding path and is injected into the bias node to cancel out the erroneous current components, thereby maintaining accurate biasing conditions.
2Ease of operation
If drain voltage depends upon current flowing through cells during program step, then programming operation is enabled, but the current varies significantly (high initially, decreases as threshold increases), making stable biasing difficult
Solution Approach 1:
The patent employs dynamic compensation by continuously adjusting the compensation current based on the actual current flowing through the memory cells during programming. As the cell current varies from high initial values to lower values as the threshold increases, the compensation mechanism dynamically adapts to maintain stable biasing conditions throughout the entire programming process.
Solution Approach 2:
The patent implements a feedback mechanism where the current flowing through the dummy decoding path is monitored and used to generate the compensation current. This feedback loop ensures that the compensation current automatically adjusts to match the varying program current, thereby maintaining stable biasing conditions despite the significant current variations inherent in the programming operation.
3Measurement precision
If compensation current is injected to balance bias current, then biasing accuracy is improved, but the circuit complexity increases with additional components
Solution Approach 1:
The patent merges the dummy decoding path with the bias generation circuitry, using the same transistor stack structure for both decoding and bias reference purposes. This integration allows the dummy path to serve dual functions: as a decoding path for memory operations and as a reference for generating compensation current, thereby reducing overall circuit complexity while maintaining high biasing accuracy.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed circuit achieves stable and accurate biasing of flash memory cells, reducing the risk of deterioration and systematic errors by isolating the dummy decoding path from temperature and process variations, ensuring consistent bias conditions during programming and read operations.
Implementation Method 1
a voltage regulator is configured to impose a reference voltage on the bias resistive divider to obtain a bias current
Implementation Method 2
a compensation stage is configured to inject into the current adder node a compensation current equal to, and of opposite sign with respect to, the bias current
Data Source
AI summary
A circuit for biasing non-volatile memory cells includes: a dummy decoding path (18) between a global bias line (33) and a biasing node (25; 125); a reference current generator (15), coupled to the dummy decoding path (18) and configured to supply a reference current (IT); a biasing stage (16, 17) configured to set a cell bias voltage (VBDC) on the biasing node (25); and a compensation stage (20), configured to compensate a current absorption of the biasing stage (16, 17) at the biasing node (25) so that the reference current (IT) will flow through the dummy decoding path (18).