Memory Cell Bias Voltage Lookup for Analog Synapse Tuning

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Solution Overview

Problem

Existing artificial neural networks face challenges in achieving high-performance information processing due to a lack of adequate hardware technology, particularly in terms of energy efficiency and the complexity of synapses, which are often bulky and inefficient in CMOS implementations.

Innovation Solution

Utilization of non-volatile memory arrays as synapses in neural networks, allowing for individual programming, erasing, and reading of memory cells with minimal disturbance, and enabling continuous analog programming for precise tuning of synapse weights.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If CMOS analog circuits are used for synapses, then neural network functionality is achieved, but the device area becomes too bulky for high-performance processing

Engineering Contradiction:
Improveinformation processing performanceVSAvoidsynapse circuit area
Core Design Contradiction:
ProductivityVSArea of stationary object

Solution Approach 1:

The patent merges the synapse weight storage function with the memory cell function by using the memory cell threshold voltage to directly represent synapse weights. This eliminates the need for separate multiplication and addition logic circuits, reducing the area required per synapse from bulky CMOS analog circuits to compact memory cells arranged in arrays.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent replaces traditional electronic multiplication and addition operations with memory cell threshold voltage characteristics. The synapse weight multiplication and neuron activation addition are performed through the natural electrical characteristics of memory cells and sense amplifiers, eliminating complex digital logic circuits.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Productivity

If digital supercomputers or GPU clusters are used, then high computational parallelism is achieved, but energy efficiency deteriorates compared to biological networks

Engineering Contradiction:
Improvecomputational parallelismVSAvoidenergy efficiency
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent implements in-situ computing where memory cells perform computational functions (multiplication and accumulation) directly at their location without requiring data movement to separate processing units. The sense amplifiers automatically perform the accumulation function, eliminating the need for separate multiply-accumulate units and reducing energy consumption associated with data transfer and processing.

Inventive Principle:
Principle #25Self-service

3Ease of operation

If separate multiplication and addition logic circuits are used, then neural network operations are performed, but device complexity and power consumption increase

Engineering Contradiction:
Improveneural network computation capabilityVSAvoidlogic circuit complexity
Core Design Contradiction:
Ease of operationVSDevice complexity

Solution Approach 1:

The patent makes memory cells universal by enabling them to perform both data storage and computational functions (multiplication and accumulation). The sense amplifiers serve dual purposes of reading memory cell data and performing the accumulation operation, eliminating the need for separate specialized circuits for each function.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS12573452B2Determination of a bias voltage to apply to one or more memory cells
Publication Date: 2026.03.10 SILICON STORAGE TECHNOLOGY INC
  • US12573452B2 patent drawing
  • US12573452B2 patent drawing
  • US12573452B2 patent drawing

AI summary

In one example, a method comprises programming a memory cell capable of storing any of N values with 1 of the N values; applying a series of currents of increasing size to a bit line of the memory cell; comparing a voltage of the bit line to a reference voltage to generate a comparison output; and when the comparison output changes value, measuring a voltage of a control gate terminal of the memory cell and storing the voltage in a bias lookup table.