Segmented Source Plates for Selective Memory Sub-Block Erase
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Solution Overview
Problem
Existing memory devices lack the ability to perform selective sub-block erase operations, as they typically erase all sub-blocks within a block simultaneously, leading to inefficiencies in data management and retention.
Innovation Solution
Implementing segmented source plates and virtual select gate switching devices at the drain-side of sub-blocks, allowing for selective control of sub-block erase operations by applying specific voltage levels to individual sub-blocks while inhibiting others, using threshold voltage programming and dummy wordlines to manage channel potential.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a common source plate is used for all sub-blocks, then the device structure is simple, but selective sub-block erase operations cannot be performed
Solution Approach 1:
The source plate is divided into multiple independent source plate segments, with each segment corresponding to a specific sub-block. This segmentation enables independent voltage control of each sub-block, allowing selective erase operations on individual sub-blocks while maintaining simple overall device architecture.
2Productivity
If all sub-blocks are erased simultaneously, then the erase operation is simple to perform, but data management efficiency deteriorates
Solution Approach 1:
The memory device is divided into multiple sub-blocks that can be independently erased. Each sub-block is associated with a specific source plate segment that can be controlled independently, enabling selective erase operations that improve data management efficiency by allowing partial erasure of only the necessary sub-blocks.
Solution Approach 2:
The device transitions from a static common source plate configuration to a dynamic segmented source plate configuration, where voltage can be dynamically applied to specific source plate segments based on erase requirements. This dynamic control enables flexible erase operations that adapt to different data management needs.
Data Source
AI summary
An example memory device includes a memory array and a processing device, operatively coupled to the memory array. The processing device is configured to: receive an erase command identifying a sub-block of a block of the memory array; cause a first voltage level to be applied to a source plate segment associated with the sub-block, thus selecting the sub-block to be erased; cause a second voltage level to be applied to a plurality of source plate segments associated with remaining sub-blocks of the block, such that the first voltage level exceeds the second voltage level by at least a predefined value; and cause a ground voltage level to be applied to one or more data wordlines of the sub-block.