Page Buffer Circuit Area Reduction via Multi-Latch Segmentation
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Solution Overview
Problem
The miniaturization of flash memory devices leads to an expansion in the area of page buffer circuits, with transistors within the page buffer reaching a miniaturization limit, preventing further size reduction while maintaining functionality.
Innovation Solution
A page buffer circuit for non-volatile semiconductor memory devices is designed with a bit line selector and multiple latches (first, second, and third) that allow simultaneous data reading and programming across multiple bit lines, reducing the overall size of the page buffer circuit without compromising action time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the flash memory is miniaturized, then the integration density is improved, but the area of the page buffer circuit expands
Solution Approach 1:
The page buffer circuit is divided into multiple functional blocks including a first latch unit, second latch unit, third latch unit, bit line selector, and control circuit. Each block performs a specific function in the data readout and programming process, allowing the overall circuit to be optimized for area while maintaining functionality.
Solution Approach 2:
The page buffer circuit is designed to handle both readout and programming operations using the same hardware resources. The latch units can store data for both readout and programming, and the bit line selector can switch between different bit lines for both operations, eliminating the need for separate buffer circuits.
2Area of stationary object
If the page buffer circuit area is reduced, then the miniaturization is improved, but the transistor size reaches a limit
Solution Approach 1:
Multiple latch units (first, second, and third latch units) are combined into a single page buffer circuit structure. The latch units work together to handle both readout and programming operations, reducing the overall circuit area while avoiding the need for further transistor miniaturization.
Solution Approach 2:
The circuit uses dynamic control signals (first control signal, second control signal, third control signal) to switch between different operational modes and bit line selections. This dynamic operation allows the circuit to perform multiple functions with fewer transistors, avoiding the miniaturization limit.
3Productivity
If multiple bit lines are accessed simultaneously, then the programming speed is improved, but the control complexity increases
Solution Approach 1:
The bit line selector is configured to select and prepare the appropriate bit line before the actual readout or programming operation. The control circuit generates control signals in advance to set up the latch units and bit line connections, enabling simultaneous access to multiple bit lines without increasing control complexity during the actual operation.
Solution Approach 2:
The control circuit acts as an intermediary that manages the complex interactions between multiple latch units, bit line selectors, and memory cells. It generates and coordinates control signals to enable simultaneous operations on multiple bit lines while keeping the overall system manageable through centralized control.
Data Source
AI summary
Within a page buffer 14 which is coupled to a non-volatile memory cell array 10 and temporally stores data as the data with a predetermined page unit is written in and read out to/from the memory cell array 10, at least one latch circuit 14v-1 including a bit line selector 14s, a page buffer unit circuit 14u including two latch L1, L2, and a latch L3 is set up for a plurality of bit lines. The bit line selector 14s selects one bit line and couples it to the page buffer unit circuit 14u. The latch L1 temporally stores the data which are read out from the memory cell of the selected bit line, and then outputs the data through the latch L2 or L3. On the other hand, the latch L1 temporally stores the programming data inputted through the latch L2 or L3, and after that outputs it to the memory cell of the selected bit line for programming.