Semiconductor Memory Pass Fail Check Circuit Overlap
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Solution Overview
Problem
Semiconductor memory devices, particularly non-volatile flash memories, face challenges in reducing program operation times and improving the reliability of pass/fail check operations due to their relatively slow write and read speeds.
Innovation Solution
Incorporating a page buffer and a pass/fail check circuit within the semiconductor memory device to control potential levels of bit lines during program and verify operations, and using a control logic to manage these circuits for enhanced pass/fail check accuracy and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If non-volatile flash memory is used to retain data without power supply, then data retention capability is improved, but write and read speeds deteriorate
Solution Approach 1:
The patent segments the memory system into multiple independent components: memory cell arrays for data storage, page buffers for temporary data holding and potential level control, and pass/fail check circuits for verification. This segmentation allows parallel operation of these components, enabling faster write and read speeds while maintaining data retention capability through the non-volatile flash memory cells.
2Productivity
If program operation time is reduced, then productivity is improved, but pass/fail check reliability may deteriorate
Solution Approach 1:
The patent applies preliminary action by performing potential level control and preliminary verification through the page buffer before the actual program operation completes. The pass/fail check circuit begins verification operations during the program pulse applying operation, allowing the check to be completed faster without sacrificing reliability, as the preliminary setup and initial verification are already in place.
Solution Approach 2:
The patent ensures continuity of useful action by overlapping the pass/fail check operation with the program pulse applying operation. The control logic coordinates these operations so that verification continues seamlessly during programming, eliminating idle time and reducing overall program operation time while maintaining continuous monitoring of program status for reliable pass/fail determination.
3Speed
If page buffer and pass/fail check circuit are added, then program operation speed is improved, but device complexity increases
Solution Approach 1:
The patent implements multi-functionality by designing the page buffer to perform multiple roles: controlling potential levels of bit lines during program operations, holding program data temporarily, and assisting in verify operations. The pass/fail check circuit similarly performs both verification during programming and standalone check operations. This multi-functionality reduces the need for separate dedicated circuits, thereby limiting the increase in device complexity while achieving faster program operation speeds.
Data Source
AI summary
A semiconductor memory device includes a memory cell array including a plurality of memory cells, a peripheral circuit performing a program pulse applying operation and a verify operation on the memory cell array, a pass/fail check circuit performing a pass/fail check operation on a program operation including the program pulse applying operation and the verify operation, and a control logic controlling the peripheral circuit and the pass/fall check circuit to perform the pass/fail check operation during the program pulse applying operation.