Depletion-Type NAND Memory Cells for Low-Power Read Operation

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Solution Overview

Problem

Existing semiconductor storage devices, particularly NAND type flash memory systems, consume a large amount of energy during write and read operations due to the use of enhancement-type transistors that require high voltage differences for read operations.

Innovation Solution

Employing depletion-type transistors in the memory cell and select transistors, where the difference between the source voltage and the second voltage is smaller than the difference between the source voltage and the first voltage, reducing the power consumption during read operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If enhancement-type transistors are used in NAND flash memory, then the memory cell can store data, but the read operation consumes large amount of energy due to high voltage difference requirements

Engineering Contradiction:

Improvepower consumption during read operationVSAvoiddata storage capability

Core Design Contradiction:

Use of energy by moving objectVSReliability

Solution Approach 1:

The patent changes the transistor type parameter from enhancement-type to depletion-type. This parameter change fundamentally alters the voltage requirements for read operations, enabling lower voltage differences while maintaining data storage capability through the different operating characteristics of depletion-type transistors

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent inverts the conventional approach by using depletion-type transistors instead of the standard enhancement-type transistors. This inversion allows the memory cell to operate with reduced voltage differences during read operations, directly addressing the energy consumption issue while preserving the essential data storage function

Inventive Principle:

Principle #13The other way round (Inversion)

2Power

If high voltage difference is applied during read operation, then the memory cell transistor conducts properly, but energy consumption increases significantly

Engineering Contradiction:

Improvevoltage difference for transistor conductionVSAvoidenergy consumption during read operation

Core Design Contradiction:

PowerVSLoss of energy

Solution Approach 1:

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent converts the inherent characteristic of depletion-type transistors (which require different voltage conditions) into a benefit for reducing energy consumption. By leveraging the unique properties of depletion-type transistors, the system achieves lower power consumption during read operations while maintaining proper transistor conduction and data storage functionality

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

Data Source

PatentUS12573459B2Semiconductor storage device having depletion-type memory cell transistors

Publication Date: 2026.03.10 KIOXIA CORP

AI summary

A semiconductor storage device has a bit line, a source line, a first memory cell and a second memory cell provided between the bit line and the source line and connected in series, a first word line connected to the first memory cell, a second word line connected to the second memory cell, and a control circuit. The control circuit, when executing a read operation with respect to the first memory cell, supplies a source voltage to the source line, supplies a first voltage to the first word line, and supplies a second voltage to the second word line, and a difference between the source voltage and the second voltage is smaller than a difference between the source voltage and the first voltage.