Read Pass Voltage Adjustment Across Shared NAND Erase Blocks
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Solution Overview
Problem
Existing memory systems face issues with read disturb in memory cells due to sensing operations, leading to increased bit error rates and data loss, as cells in one block are disturbed by operations on neighboring cells within the same block, particularly exacerbated by repeated program/erase cycles.
Innovation Solution
Implementing a method to adjust the read pass voltage dynamically based on the time-after-programming and other factors, such as P/E cycles and temperature, to mitigate read disturb in victim erase blocks by applying a reduced read pass voltage during operations on aggressor blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a fixed read pass voltage is applied during sensing operations, then the read operation is simple and fast, but read disturb occurs in victim cells leading to increased bit error rates
Solution Approach 1:
The patent applies dynamics by transitioning from a fixed read pass voltage to a dynamic voltage adjustment mechanism. The read pass voltage is modified based on the time-after-programming of victim cells and the number of P/E cycles, allowing the voltage to adapt to changing cell conditions and minimize read disturb while maintaining read operation efficiency
Solution Approach 2:
The patent changes the parameter of read pass voltage dynamically. By adjusting the read pass voltage according to time-after-programming and P/E cycle counts, the system optimizes the voltage level to reduce read disturb effects on victim cells, thereby lowering bit error rates without significantly impacting read speed
2Adaptability or versatility
If repeated program/erase cycles are performed, then data can be updated and modified, but threshold voltages of cells shift leading to increased read disturb
Solution Approach 1:
The patent implements feedback by monitoring time-after-programming and P/E cycle counts, then using this information to adjust the read pass voltage. This feedback mechanism compensates for threshold voltage shifts caused by repeated programming and erasing operations, maintaining data integrity throughout the cell's operational life
Solution Approach 2:
The patent applies preliminary action by proactively adjusting the read pass voltage before read disturb can cause significant errors. By modifying the voltage based on predicted cell aging (time-after-programming and P/E cycles), the system prevents read disturbances from accumulating to problematic levels
3Reliability
If read pass voltage is reduced to minimize read disturb, then bit error rates decrease, but read operation speed and reliability may be compromised
Solution Approach 1:
The patent uses dynamics to adjust the read pass voltage based on actual cell conditions. Rather than using a permanently reduced voltage, the system dynamically modifies the voltage level according to time-after-programming and P/E cycle counts, optimizing the balance between read speed and data integrity at each stage of cell aging
Data Source
AI summary
An apparatus can comprise a memory array comprising multiple erase blocks coupled to a same plurality of strings of memory cells. A controller is configured to: apply a first read pass voltage to unselected access lines of the first group of access lines in association with performing a sensing operation on a selected access line of the first group of access lines; and determine a second read pass voltage to be applied to the second group of access lines in association with performing the sensing operation on the selected access line of the first group. The second read pass voltage is determined by: determining an amount of time that the second group of memory cells has been in a programmed state; or performing a scan to determine a threshold voltage (Vt) characteristic corresponding to the second group of memory cells; or both.