Strobe Generation Unit for DDR Semiconductor Power Reduction
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Solution Overview
Problem
Semiconductor devices with DDR function in their I/O circuits face issues with power consumption and data quality due to timing shifts in clock signals, leading to inferior data writes.
Innovation Solution
A semiconductor device design that includes a first latch unit for write data latching based on a strobe signal, a second latch unit for data transfer to a buffer using a first clock signal, and a strobe generation unit with bit shift counters and logic gates to generate strobe signals, reducing power consumption and improving data writes by controlling the latch period and clock signal timing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If clock signal timing is adjusted to improve data write quality, then data write quality improves, but power consumption increases due to additional clock signal distribution
Solution Approach 1:
The patent extracts the strobe signal generation function from the global clock distribution system. Instead of distributing multiple clock signals (CK_t, CK_c, DQS_t, DQS_c) throughout the device, the strobe generation unit locally generates strobe signals from the received DQS_t signal, eliminating the need for extensive clock signal distribution trees and reducing power consumption while maintaining data write quality.
Solution Approach 2:
The strobe signal acts as an intermediary between the external DQS_t clock signal and the internal latch circuitry. The strobe generation unit uses the DQS_t signal to generate synchronized strobe signals (S1, S2, S3, S4) that coordinate data latching without requiring direct distribution of multiple clock signals to all latch units, thereby reducing power consumption while ensuring proper timing.
2Measurement precision
If multiple clock signals are distributed to ensure proper timing, then timing precision improves, but device complexity increases
Solution Approach 1:
The patent extracts the timing control function from the global clock distribution network and localizes it to the strobe generation unit. By generating strobe signals locally from the received DQS_t signal, the system eliminates the need for complex global clock distribution while maintaining precise timing control at each latch unit through the generated strobe signals.
Solution Approach 2:
The strobe generation unit performs multiple functions: it receives the DQS_t signal, generates four phased strobe signals (S1, S2, S3, S4) for coordinating data latching across multiple latch units, and ensures proper timing synchronization. This multi-functional unit replaces what would otherwise require separate clock distribution networks, reducing device complexity while maintaining timing precision.
Data Source
AI summary
A semiconductor device includes a first latch unit that latches write data based on a strobe signal, a second latch unit that receives the write data latched in the first latch unit based on a first clock signal, and a strobe generation unit that generates the strobe signal and supplies it to the first latch unit. The strobe generation unit includes a bit shift counter, which receives a second clock signal and outputs a bit shift signal having a logic level that is inverted every plural clock cycles of the second clock signal, and a logic gate that outputs the second clock signal as the strobe signal according to the bit shift signal. The latch period of the write data in the first latch part is determined by the period of the strobe signal and also the period of the bit shift signal.