Variable Polarity Line Decoder for Non-Volatile Memory
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Solution Overview
Problem
Conventional line decoders for CMOS semiconductor memory arrays face limitations in simultaneously applying high negative and positive voltages due to transistor breakdown voltage restrictions, leading to erasing stress and increased complexity in memory cell management.
Innovation Solution
A line decoder architecture with drivers in separate wells, utilizing MOS transistors of different conductivity types, and a predecoder to generate selection signals for variable polarity, allowing for voltage differences greater than transistor breakdown voltage between control lines, thereby neutralizing erasing stress without sectorization of the memory array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional line decoder uses MOS transistors to simultaneously supply negative and positive voltages to control lines, then the voltage difference is limited to the breakdown voltage of the transistors (typically 10V-11V), but this limitation prevents application of high negative voltages (e.g., -10V) and high positive voltages (e.g., +10V) simultaneously, causing erasing stress on memory cells
Solution Approach 1:
The line decoder is divided into multiple independent decoder units, each dedicated to a specific control line. Each decoder unit contains its own MOS transistors that are independently biased, allowing different voltage ranges to be applied to different control lines simultaneously without mutual interference, thus eliminating erasing stress while maintaining high voltage capability
Solution Approach 2:
Independent decoder units act as intermediaries between the voltage supply and control lines. Each decoder unit independently manages its own voltage supply and control line, mediating the voltage application to ensure that high negative and positive voltages can be applied to different lines simultaneously without exceeding transistor breakdown limits in any single unit
2Reliability
If sector-erasable memory array architecture with multiple isolated wells is used to apply different voltages to different sectors, then erasing stress is eliminated, but the semiconductor surface area occupied is much greater than that of an undivided memory array
Solution Approach 1:
The line decoder functionality is segmented into multiple independent decoder units that can be densely integrated within the same semiconductor substrate. This segmentation allows voltage control to be distributed without requiring physical sector isolation, maintaining compact layout while enabling independent voltage control for erasing stress management
Solution Approach 2:
Multiple decoder units are merged into a single integrated decoder structure that shares common substrate and interconnect resources. This merging allows the system to achieve the voltage control benefits of sectorized architecture while maintaining the area efficiency of an undivided memory array through resource sharing and compact integration
Data Source
AI summary
The present disclosure relates to a memory including a memory array with at least two rows of memory cells, a first driver coupled to a control line of the first row of memory cells, and a second driver coupled to a control line of the second row of memory cells. The first driver is made in a first well, the second driver is made in a second well electrically insulated from the first well, and the two rows of memory cells are produced in a memory array well electrically insulated from the first and second wells.