3D Storage Architecture with Tier-Specific Timing Control
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Solution Overview
Problem
Three-dimensional integrated circuit (3DIC) constructions face challenges in self-timing and voltage control due to thermal and process variations across multiple semiconductor die tiers, leading to timing coordination errors and performance variations during memory operations.
Innovation Solution
A storage circuit architecture with multiple tiers of semiconductor dies, each equipped with a timing circuit and replica/dummy word line-driven tracking cells, uses tier-specific trim bits and global timing signals to independently control timing and voltage states, accounting for inter-tier variations and optimizing memory operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a 3DIC construction is used to reduce overall area and signal propagation times, then area and speed are improved, but self-timing and voltage control become more difficult due to inter-tier process and thermal variations
Solution Approach 1:
The patent divides the timing control system into tier-specific segments. Each tier has its own timing circuit and trim bits, allowing independent timing adjustment for each tier. This segmentation enables precise control of signal propagation in each tier while managing the overall complexity through modular design.
Solution Approach 2:
The patent applies local quality by providing tier-specific trim bits and timing circuits that are optimized for each individual tier's characteristics. Each tier receives customized timing control based on its specific process and thermal conditions, rather than using a uniform timing approach across all tiers.
2Quantity of substance
If multiple tiers are used to form storage arrays, then storage density is improved, but timing coordination errors increase due to inter-tier variations
Solution Approach 1:
The patent incorporates feedback mechanisms through trim bits that can be adjusted based on measured timing characteristics of each tier. The timing circuits monitor and respond to inter-tier variations, allowing dynamic adjustment to maintain accurate timing coordination across all tiers despite process and thermal variations.
Solution Approach 2:
The patent changes timing parameters individually for each tier using tier-specific trim bits. By adjusting timing parameters (such as access time, precharge time, and data hold time) independently for each tier, the system compensates for inter-tier variations and maintains reliable timing coordination across the entire 3D storage array.
Data Source
AI summary
A three-dimensional (3D) storage circuit includes two or more tiers of semiconductor dies, and a storage array of bitcells distributed on the two or more tiers to form a plurality of storage subarrays. One of the storage subarrays is arranged on a respective one of the tiers. Row and column replica/dummy tracking cells are arranged on each of the tiers. A timing circuit is coupled to the tracking cells of each of the tiers. In response to receipt of tier-specific trim bits for each of the tiers, the timing circuit independently controls a timing and/or voltage state of each of the tiers during an access operation of the 3D storage circuit to account for process and/or thermal variation between tiers of the 3D storage circuit.