Digital Storage TRIZ Cases

A differential compute-in-memory bitcell uses cross-coupled inverters and capacitors to perform multiply-and-accumulate operations within memory.

Segmented multiplexers reduce layout area and chip size by distributing drivers along global input-output lines.

A self-refresh timing circuit generates a clock signal to control memory bank refresh operations.

A magnetic memory device merges spin-transfer and spin-orbit torque effects for efficient data writing.

A sense amplifier uses negative source voltage pulsing to maintain gate-source terminal voltage above threshold levels.

A memory array design switches bit cells between nominal and retention voltage levels using a dedicated select circuit.

Tier-specific trim bits adjust voltage and timing states per tier, compensating for inter-layer process and thermal variations.

A memory array architecture uses selector circuits to couple a single sense amplifier to two digit line matrices, reducing component count.

Dynamic power fill circuits execute dummy operations to stabilize voltage and prevent damage from high-frequency current fluctuations.

Segmented power rails allow independent voltage control, improving signal integrity during high-speed memory operations.

A refresh control device generates non-constant cycle triggers to arbitrate memory access requests.

A voltage regulator circuit tracks SRAM bitcell leakage current and threshold voltage to supply a proportional standby power level.

A semiconductor memory architecture uses pre-fetch registers to store data units for sequential processing by shared sense amplifiers and write drivers.

Period code generation and synthesis circuits control buffer inactivation signals, resolving I/O complexity while stabilizing data strobe input phases.

A semiconductor memory apparatus adjusts serial data sequencing through dynamic delay code generation and timing control blocks.

Position-based reference signal correction compensates for wiring parasitic resistance to maintain measurement accuracy across the memory cell array.

A register clock driver uses multi-stage training to adjust sampling timing.

A data path interface uses programmable delay units and align blocks to synchronize data across clock domains.

A level-shifting pulse latch inverts and transfers system clock signals to memory power domains using a pass transistor.

A semiconductor memory termination circuit switches reference voltages between POD and open terminal modes.

Varying threshold voltages across memory cells improve read speed and write margin in static random access memory arrays.

A semiconductor memory device uses a dummy word line to write test data for independent evaluation of normal word lines.

Address control circuit delays commands via multiple paths to store addresses in local buffers.

A clock locking protocol aligns memory frames with periodic signals to enable precise synchronization without complex header circuits.

A controlling device adjusts write current conduction periods to match ideal set mode resistance across phase change storage elements.

A reverse scrambler calculates aggressor row addresses to adjust victim word line data during memory operations.

Independent precharging control prevents peak current and noise during high-speed data transmission, ensuring stable circuit operation.

A dual-gate oxide semiconductor transistor manages threshold voltage through independent gate potentials to control off-state current.

A magnetic tunnel junction with a gadolinium oxide barrier uses voltage-controlled interlayer coupling to switch magnetization states.

Repair circuit segments address decoding paths to enable simultaneous testing of normal and redundancy column lines.

Built-in self-test controller detects hardware failures in memory sub-arrays using periodic test operations to address endurance limitations.

A solid state selector device with non-linear current-voltage response integrates with memory cells to mitigate leakage.

A memory controller generates addresses for specific bank rows to execute targeted refresh operations within a DRAM storage array.

Resistor-based voltage division replaces transistor matching to resolve sensing ratio inaccuracies in memory read operations.

Separating field generation from write current reduces switching density and prevents insulating spacer damage in magnetic memory arrays.

Opposite polarity pulses enable accurate state determination during read operations, reducing control unit complexity.

A nonvolatile SRAM cell uses a three-terminal magnetoresistive element to store data without power.

Integrating phase change memory and magnetoresistive random access memory arrays resolves the tradeoff between data storage density and access speed.

A semiconductor phase controller shifts data strobe signal phases to support multiple input output modes.

Interleaved addressing distributes program and erase cycles across multiple memory ports, reducing read latency while extending non-volatile cell lifespan.

Adaptive setting method adjusts resistive memory cell operations based on verifying results to maintain oxygen vacancy region stability.

A memory controller switches write targets between SLC and MLC modes based on queue depth thresholds.

Bundling refresh and calibration commands reduces arbiter load, resolving sequential arbitration bottlenecks.

A semiconductor memory data alignment circuit uses pipeline registers to latch addresses at different intervals for high-speed serial conversion.

Oscillating voltage waveforms reduce device complexity by eliminating multiple steady-state voltage levels while maintaining programming precision.

A write disturb detect circuit monitors word line activation states to identify simultaneous port operations in multi-port memory cells.

Parallel capacitor structures accumulate binary summations to detect bit errors, eliminating digital conversion latency and reducing circuit complexity.

A TL-TCAM cell circuit uses segmented storage to reduce parasitic capacitance and improve search speed.