Dual-Gate Oxide Semiconductor Memory Device for Data Retention
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Solution Overview
Problem
Existing oxide semiconductor transistors in DRAMs face issues with data retention time and reliability due to potential applied to the back gate affecting electrical characteristics, often requiring high potentials that can lower transistor reliability.
Innovation Solution
A memory device with a driver circuit that applies a first potential lower than the source and drain potential to the first gate and a second potential lower than both to the second gate, using a metal oxide in the channel formation region, particularly containing In, Zn, and optionally Ga, to manage the threshold voltage and reduce off-state current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of moving object
If a high potential is applied to the back gate to reduce off-state current, then data retention time is improved, but transistor reliability deteriorates
Solution Approach 1:
The gate is divided into two separate gates: a front gate and a back gate. This segmentation allows independent control of threshold voltage and off-state current, enabling optimization of both data retention time and transistor reliability without compromising either parameter.
2Object-generated harmful factors
If a high potential is applied to the back gate to shift threshold voltage, then off-state current is reduced, but electric field stress increases
Solution Approach 1:
Different potentials are applied to different regions (front gate and back gate) to achieve localized control. The front gate potential controls threshold voltage while the back gate potential controls off-state current, allowing each region to optimize its function without generating excessive electric field stress elsewhere in the transistor.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a memory device with enhanced data retention time and high reliability by reducing off-state current and electric field stress, ensuring long-term data retention and improved transistor reliability.
Implementation Method 1
a memory device that can function by utilizing semiconductor characteristics
Data Source
AI summary
A memory device having long data retention time and high reliability is provided. The memory device includes a driver circuit and a plurality of memory cells, the memory cell includes a transistor and a capacitor, and the transistor includes a metal oxide in a channel formation region. The transistor includes a first gate and a second gate, and in a period during which the memory cell retains data, negative potentials are applied to the first gate and the second gate of the transistor.