Semiconductor Memory Data Alignment Control Circuit
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Solution Overview
Problem
Conventional semiconductor memory apparatuses face issues with correctly sequencing serial data when converting parallel data due to variations in delay times, leading to potential output of wrongly sequenced serial data.
Innovation Solution
The semiconductor memory apparatus incorporates a data alignment control signal generation unit, a timing control block, a delay time control block, and a data alignment unit to generate and manage delay codes, ensuring accurate sequencing of serial data by adjusting delay times and changing data sequences based on tuning mode signals and count pulses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the latch section latches the delay control signal to output the timing control signal, then the data alignment function is achieved, but if the delay time of the delay section deviates from the preset delay time, the serial data sequencing becomes incorrect
Solution Approach 1:
The patent introduces a feedback mechanism where the delay time control block receives the timing control signal and delay control signal, compares their phases, and adjusts the delay codes accordingly. This closed-loop feedback system automatically compensates for delay time deviations, ensuring the latch section operates with precise timing control and maintaining correct serial data sequencing.
Solution Approach 2:
The patent dynamically adjusts the delay parameter (delay codes) based on phase comparison results. The delay time control block modifies the delay codes to change the delay amount, allowing the system to adapt to timing variations and maintain accurate data alignment despite initial deviations in delay time.
2Adaptability or versatility
If a fixed delay time is used in the delay section, then the circuit design is simple, but the system cannot adapt to timing variations and may output wrongly sequenced data
Solution Approach 1:
The patent transforms the static fixed delay time into a dynamic adjustable parameter. The delay section's delay amount is no longer fixed but can be dynamically changed through the delay time control block, which adjusts delay codes based on phase comparison. This enables the system to adapt to different timing requirements while maintaining a relatively simple overall circuit structure.
Solution Approach 2:
The system performs self-adjustment through the automatic feedback mechanism. The delay time control block automatically compares phases and adjusts delay codes without external intervention, allowing the system to self-correct timing deviations and maintain optimal performance adaptively.
3Reliability
If the delay amount is increased to compensate for timing variations, then data alignment may be improved, but the delay control signal phase may no longer match the data output control signal timing
Solution Approach 1:
The feedback mechanism continuously monitors the phase relationship between the delay control signal and the data output control signal. When the delay amount is adjusted to improve data alignment, the feedback system detects any resulting phase mismatch and automatically adjusts the delay codes to restore proper timing synchronization, preventing the harmful effect of timing desynchronization.
Data Source
AI summary
A semiconductor memory apparatus includes a data alignment control signal generation unit configured to output a data alignment control signal by generating a pulse when a tuning mode signal is enabled, and generate the data alignment control signal as a count pulse is inputted after the data alignment control signal generated by the tuning mode signal is outputted; a timing control block configured to determine a delay amount according to delay codes, generate a delay control signal by delaying the data alignment control signal, and output a timing control signal by latching the delay control signal at an enable timing of a data output control signal; a delay time control block configured to generate the delay codes; and a data alignment unit configured to convert parallel data into serial data, and change a data sequence of the serial data in response to the timing control signal.