On-Demand Memory Write Mode for Queue Depth Management
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Solution Overview
Problem
Conventional memory systems face performance and endurance issues due to the need for constant operation in high-performance SLC memory mode, leading to increased program and erase cycles, reduced device endurance, and increased cost and size, while direct writing to MLC/TLC/QLC memory is often too slow to meet performance requirements.
Innovation Solution
Implementing an on-demand high performance mode for memory write commands, where data is written to SLC memory only when performance requirements are high, indicated by a queue depth threshold, and otherwise written to MLC/TLC/QLC memory, using a performance mode component to manage the switching between modes based on the number of memory write commands in the queue.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data is always written to SLC memory to ensure high write performance, then write speed is improved, but program and erase cycles increase, reducing device endurance and increasing cost and size
Solution Approach 1:
The system dynamically switches between SLC and MLC/TLC/QLC memory modes based on real-time queue depth monitoring. When the queue depth exceeds a threshold, the system activates SLC memory for high-performance writing; when the queue depth is below the threshold, it switches to MLC/TLC/QLC memory for normal operation. This dynamic adaptation resolves the contradiction by providing high write speed only when necessary, thereby preserving device endurance.
Solution Approach 2:
The system changes the memory writing parameter (memory mode) based on queue depth conditions. By monitoring the number of pending write commands and comparing it to a threshold, the system adjusts the memory mode between SLC (high performance) and MLC/TLC/QLC (low power/size). This parameter change allows the system to optimize between write speed and device endurance based on actual workload conditions.
2Productivity
If SLC memory is used continuously for high performance writing, then write performance is maintained, but device size and cost increase
Solution Approach 1:
The system dynamically activates SLC memory only when queue depth exceeds the threshold, rather than maintaining SLC memory continuously. This dynamic approach allows the memory device to maintain smaller size by using SLC memory temporarily only when high write performance is needed, while relying on MLC/TLC/QLC memory for normal capacity storage.
Solution Approach 2:
The memory device achieves multi-functionality by using the same physical memory cells for different purposes at different times. The SLC memory region serves dual purposes: it acts as high-performance write buffer when queue depth is high, and returns to normal capacity mode when queue depth is low. This universality allows the device to maintain smaller size while still providing high performance when needed.
3Reliability
If the system monitors queue depth and switches between SLC and MLC/TLC/QLC modes, then write amplification is reduced and endurance is improved, but system complexity increases
Solution Approach 1:
The system implements feedback control by continuously monitoring the queue depth of pending write commands and using this information to determine the appropriate memory mode. The controller compares the current queue depth against a predefined threshold and adjusts the memory mode accordingly. This feedback mechanism automates the decision-making process, reducing the need for complex control logic while maintaining optimal performance and endurance.
Data Source
AI summary
A processing device in a memory system determines whether a number of pending memory commands satisfies a threshold criterion. Responsive to the number of pending memory commands satisfying the threshold criterion, the processing device initiates a first mode of operation for the system and writes, in the first mode of operation, data corresponding to at least a subset of the number of pending memory commands to a first portion of the memory device.