Semiconductor Memory Architecture Using Pre-fetch Registers
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Solution Overview
Problem
Resistive memory devices require a large area for sense amplifiers and write drivers due to the need for numerous processing blocks to handle large data processing, leading to inefficient layout and increased size.
Innovation Solution
A semiconductor device with a reduced number of sense amplifiers and write drivers is implemented by using a memory cell array with non-volatile memory cells, registers for storing pre-fetch unit data, and a write driver circuit that writes data sequentially, along with a sense amplifier circuit that amplifies and stores data in registers during read and write operations, utilizing a time division method to process data in pre-fetch units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a large number of sense amplifiers and write drivers are used to process large amounts of data (512 bytes to 4 Kbytes) at one time, then data processing capability is improved, but the area occupied by the sense amplifier and write driver block increases
Solution Approach 1:
The patent divides data processing into pre-fetch units that are processed sequentially through multiple cycles. Instead of processing all data simultaneously with numerous parallel sense amplifiers and write drivers, the data is segmented into smaller units (e.g., 64-byte pre-fetch units) that are handled one at a time, reducing the number of required processing blocks while maintaining overall data processing capability.
Solution Approach 2:
The patent introduces a pre-fetch mechanism where data is preliminarily loaded into pre-fetch buffers before being processed by the sense amplifiers and write drivers. This preliminary action allows the main processing blocks to work sequentially on smaller data units rather than handling large data blocks simultaneously, thereby reducing the area requirement for processing blocks while maintaining high data processing throughput.
2Area of stationary object
If the number of sense amplifiers and write drivers is decreased to reduce area, then area efficiency is improved, but data processing capability may be reduced
Solution Approach 1:
The patent ensures continuous data processing by implementing a multi-cycle operation where pre-fetch buffers continuously supply data units to the sense amplifiers and write drivers. While one pre-fetch unit is being processed, the next unit is being pre-fetched, maintaining continuous useful action without idle processing blocks, thus preserving data processing capability with fewer processing blocks.
Solution Approach 2:
The patent implements dynamic control of the sense amplifiers and write drivers through cycle-based enable signals. The processing blocks are dynamically activated for specific pre-fetch units and disabled when not needed, allowing the same blocks to handle different data units at different times. This dynamic operation enables fewer processing blocks to achieve the same overall data processing capability as more blocks operating in parallel.
Data Source
AI summary
A semiconductor device having an architecture for reducing an area is provided. The semiconductor device includes a memory cell array including a plurality of non-volatile memory cells, a plurality of registers each configured to store pre-fetch unit data, and a write driver circuit configured to write pre-fetch unit data sequentially output from the plurality of registers to the memory cell array during a write operation. The semiconductor device also includes a sense amplifier circuit configured to sense and amplify pre-fetch unit data sequentially output from the memory cell array and to sequentially store the amplified pre-fetch unit data in the plurality of registers, respectively, during a read operation.