Selective DRAM Refresh via Bank and Row Addressing
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Solution Overview
Problem
Current DRAM refresh methods consume significant system resources and power due to the need for frequent refresh operations, especially as integration density increases, leading to longer refresh times and higher power consumption, which contradicts the demand for faster processing and lower power usage in computers.
Innovation Solution
A DRAM refresh method and apparatus that allows for selective refreshing of specific locations within a DRAM storage array, using a memory controller to generate refresh instructions and instructions that identify which rows need to be refreshed, thereby reducing unnecessary refresh operations and optimizing refresh timing and power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If DRAM refresh operations are performed frequently to ensure data integrity, then data reliability is improved, but power consumption increases
Solution Approach 1:
The DRAM storage array is divided into multiple banks, and each bank is further divided into multiple rows. The refresh operation selectively targets specific rows within specific banks based on the refresh instruction, rather than refreshing the entire storage array. This segmentation allows the system to maintain data integrity for only the necessary portions of memory, significantly reducing power consumption compared to full-array refresh operations.
Solution Approach 2:
The refresh operation applies different treatment to different regions of the DRAM storage array. Based on the refresh instruction containing bank address and row address information, the system performs refresh operations only on the specified local region (specific bank and row), while leaving other regions unchanged. This local quality approach ensures that power consumption is concentrated only where data integrity is currently needed.
2Reliability
If DRAM refresh operations are performed frequently to ensure data integrity, then data reliability is improved, but system processing speed deteriorates
Solution Approach 1:
By segmenting the refresh operation to target only specific banks and rows rather than the entire storage array, the system reduces the time required for each refresh cycle. The refresh instruction contains precise address information that allows the memory controller to quickly locate and refresh only the necessary data regions, minimizing the time that refresh operations occupy system resources and allowing faster processing to proceed concurrently.
Solution Approach 2:
The system performs a partial refresh operation, refreshing only the specific portion of the DRAM storage array that is indicated by the refresh instruction, rather than performing a complete refresh of all rows in all banks. This partial action approach maintains data integrity for the critical region while avoiding the time penalty of refreshing unnecessary regions, thereby improving overall processing speed.
3Reliability
If full DRAM storage array refresh is performed, then data integrity is ensured, but refresh time increases
Solution Approach 1:
The refresh operation is segmented to target only the specific bank and row indicated by the refresh instruction. The memory controller extracts the bank address and row address from the refresh instruction, then performs the refresh operation only on that specific segment of the storage array. This segmentation dramatically reduces refresh time compared to refreshing the entire array, while still ensuring data integrity for the targeted region.
Solution Approach 2:
The invention extracts the essential refresh operation from the context of a full-array refresh and applies it only to the necessary portion of the DRAM storage array. By taking out only the specific bank and row that need refreshing (as identified by the refresh instruction), the system eliminates the time-consuming aspect of refreshing unnecessary regions while maintaining data integrity where it matters.
4Reliability
If full DRAM storage array refresh is performed, then data integrity is ensured, but system resource consumption increases
Solution Approach 1:
The refresh instruction contains segmented address information (bank address and row address) that allows the memory controller to precisely locate and refresh only the necessary portion of the storage array. This segmentation approach reduces system resource consumption by avoiding unnecessary access to and manipulation of unrelated memory regions, thereby reducing the overall complexity and resource burden of the refresh operation.
Solution Approach 2:
The system applies local quality by concentrating refresh resources only on the specific bank and row indicated by the refresh instruction. Rather than distributing refresh operations across the entire storage array, the system focuses computational and temporal resources on the local region that requires refreshing, thereby reducing overall system resource consumption while maintaining data integrity for the critical region.
Data Source
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AI summary
A DRAM refresh method, apparatus, and system are provided. A to-be-refreshed area in a refresh block is specified in a refresh instruction, so as to refresh a specified location of a DRAM storage array. The method includes: receiving, by a DRAM refresh apparatus, a refresh instruction from a memory controller, where the refresh instruction includes an identifier of a to-be-refreshed block and refresh information used to indicate a to-be-refreshed area, and the refresh instruction is used to instruct the DRAM refresh apparatus to refresh the to-be-refreshed area in the to-be-refreshed block (S902); generating, by the DRAM refresh apparatus, addresses of to-be-refreshed bank rows in the to-be-refreshed block according to the identifier and the refresh information (S904); and refreshing, by the DRAM refresh apparatus, locations corresponding to the addresses of the bank rows in the to-be-refreshed block (S906). In this way, a DRAM refresh time is shortened, refresh power consumption is reduced, a refresh operation is more flexible, and system resource consumption is reduced while data integrity is ensured.