Multi-port SCM Interface with Interleaved Addressing
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Solution Overview
Problem
Current memory subsystems face limitations in memory capacity, latency, and data granularity, which affect computing system performance, and existing memory technologies struggle with high power consumption, cost, and limited endurance of non-volatile memory cells.
Innovation Solution
A multi-port storage-class memory interface is introduced, utilizing 3DXP memory dice and a wear-leveling operation to distribute program and erase cycles across memory cells, enabling low latency, high bandwidth, and efficient data transfer with interleaved address schemes and distributed cache configurations to manage wear levels and improve memory subsystem performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If non-volatile memory cells are used to increase memory capacity and provide non-volatility, then data persistence is improved, but power consumption and manufacturing cost increase
Solution Approach 1:
The memory subsystem is divided into multiple memory devices (e.g., NAND flash memory devices) organized in a distributed architecture. Each memory device operates independently but contributes to the overall non-volatile storage capacity, allowing the system to achieve data persistence while managing power consumption through selective activation of memory devices based on workload requirements
2Quantity of substance
If non-volatile memory cells are used to increase memory capacity, then storage capacity is improved, but manufacturing cost increases
Solution Approach 1:
The system combines multiple types of memory technologies (e.g., NAND flash memory with other non-volatile memory devices) in a unified memory subsystem architecture. This merging approach allows the system to achieve high storage capacity by leveraging the strengths of different memory technologies while distributing manufacturing costs across multiple device types and suppliers, thereby reducing overall system cost
3Device complexity
If single-port memory interface is used, then device complexity is low, but read latency and data transfer speed are limited
Solution Approach 1:
The memory interface is segmented into multiple independent ports (first port and second port) that can simultaneously handle different memory operations. Each port has dedicated control logic and data paths to memory devices, enabling parallel read and write operations. This segmentation reduces read latency by allowing multiple data transfers to occur concurrently while keeping each individual port relatively simple in design
4Device complexity
If memory operations are concentrated in single location, then device complexity is low, but productivity and data transfer bandwidth are limited
Solution Approach 1:
The memory subsystem transitions from a single-location operation model to a distributed multi-device architecture. Memory devices are organized across multiple dimensions (different memory chips, memory stacks, or memory modules) and accessed through multiple ports simultaneously. This dimensional expansion enables parallel data transfer operations, significantly increasing overall bandwidth while maintaining relatively simple control logic at each access point through the use of interleaved addressing schemes
Data Source
AI summary
Methods, systems, and devices for a multi-port storage-class memory interface are described. A memory controller of the storage-class memory subsystem may receive, from a host device, a request associated with host addresses. The memory controller may generate interleaved addresses with a low latency based on the host addresses. The interleaved addresses parallelize processing of the request utilizing a set of memory media ports. Each memory media port of the set of memory media port may operate independent of each other to obtain a desired aggregated data transfer rate and a memory capacity. The interleaved address may leave no gaps in memory space. The memory controller may control a wear-leveling operation to distribute access operations across one or more zones of the memory media port.