Memory Array Architecture with Dual Matrix Sense Amplifier Bridge
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Solution Overview
Problem
The efficiency of semiconductor memory cell sub-arrays is sub-optimal due to limited data line length caused by the large capacitance of sense amplifiers and data lines, which occupies valuable real estate and limits the ability to register voltage accurately, especially as devices are scaled smaller.
Innovation Solution
Implementing a memory cell sub-array architecture with two matrices and a single sense amplifier connected via a bridge, using selector circuitry like a multiplexor to drive both matrices, reducing the number of sense amplifiers and minimizing capacitance coupling, allowing one sense amplifier to drive two matrices efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a single sense amplifier services one data line, then voltage registration accuracy is maintained, but valuable real estate is occupied and array efficiency is reduced
Solution Approach 1:
The sense amplifier is designed to service multiple data lines (specifically two matrices) through the shared data line architecture, allowing a single sense amplifier to perform the voltage registration function for multiple capacitors across different matrices, thereby improving array efficiency while maintaining measurement precision
2Productivity
If data lines are made longer to service more capacitors, then array efficiency improves, but voltage registration accuracy deteriorates due to capacitance coupling
Solution Approach 1:
An intermediate capacitor is introduced between the data line and the sense amplifier to isolate and decouple the capacitance effects. This intermediary element allows longer data lines to service more capacitors while preventing capacitance coupling from degrading the voltage registration accuracy at the sense amplifier
3Productivity
If the number of sense amplifiers is reduced to free up real estate, then array efficiency improves, but the ability to service multiple matrices deteriorates
Solution Approach 1:
The sense amplifier is configured with the capability to service multiple matrices through the shared data line architecture, allowing a single sense amplifier to perform voltage registration for capacitors across different matrices, thereby reducing the total number of sense amplifiers needed while maintaining the ability to service multiple matrices
4Area of moving object
If capacitor size is reduced during scaling, then device size decreases, but charge capability deteriorates limiting data line service ability
Solution Approach 1:
The intermediate capacitor acts as a charge reservoir that compensates for the reduced charge capability of smaller capacitors. By introducing this intermediary element, the system can maintain adequate charge levels on the data line even when individual capacitors are smaller, thereby enabling proper sensing operation in scaled-down devices
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases memory cell sub-array efficiency by reducing the number of sense amplifiers by approximately 50%, freeing up valuable real estate for additional storage components and enabling longer digit lines without compromising voltage registration accuracy.
Implementation Method 1
The change in voltage is typically registered by the sense amplifier, which may categorize the change in voltage as indicating either that the capacitor is storing a 0 or a 1.
Implementation Method 2
the memory cell sub-array may include a storage device, such as a capacitor, that communicates with a sense amplifier through a data line... the capacitor stores data with its charge state
Data Source
AI summary
An apparatus may include a first matrix comprising a first plurality of digit lines, a second matrix comprising a second plurality of digit lines, a plurality of sense amplifiers, and a plurality of selector circuits. Each selector circuit of the plurality of selector circuits may be configured to selectively couple a respective sense amplifier to either a first digit line of the first plurality of digit lines or a second digit line of the second plurality of digit lines.