Self-Refresh Timing Circuit for DRAM Power Optimization

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Solution Overview

Problem

Conventional semiconductor memory devices face high power consumption due to the continuous activation of temperature sensors for self-refresh mode adjustments, which is not optimized for reducing current consumption.

Innovation Solution

A self-refresh timing circuit that includes a temperature sensor, reference voltage source, comparison circuit, enable circuit, and oscillation circuit, which generates a self-refresh clock signal to control the operating frequency of the bank address generator and counter, and activates only when necessary to adjust the refresh period based on temperature and completed refresh operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If the temperature sensor is always activated to detect temperature for self-refresh mode adjustments, then the refresh period can be optimized according to temperature, but the total power consumption of the DRAM memory device increases

Engineering Contradiction:
Improvetemperature-dependent refresh period adjustmentVSAvoidtotal power consumption
Core Design Contradiction:
Adaptability or versatilityVSUse of energy by moving object

Solution Approach 1:

The enable circuit activates the temperature sensor and comparison circuit only at specific periodic intervals when self-refresh mode is entered or exited, rather than keeping them continuously active. This periodic activation allows temperature-based refresh period optimization to occur at critical transition points while minimizing overall power consumption by keeping these circuits inactive during normal operation.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The self-refresh timing circuit automatically adjusts the refresh period based on temperature sensing without requiring continuous external control signals. Once enabled, the circuit self-regulates by comparing temperature sensor output with reference voltage and automatically generating appropriate clock signals for the bank address generator and self-refresh counter, reducing the need for continuous external intervention and lowering power consumption.

Inventive Principle:
Principle #25Self-service

2Productivity

If the comparison circuit and oscillation circuit are continuously activated, then the self-refresh clock signal can be continuously generated to control refresh operations, but the power consumption increases

Engineering Contradiction:
Improveself-refresh operation controlVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The enable circuit generates periodic enable signals that activate the comparison circuit and oscillation circuit only when needed - specifically when entering or exiting self-refresh mode. This periodic activation ensures that the self-refresh clock signal is generated at the appropriate times to maintain memory refresh operations while keeping the comparison and oscillation circuits inactive during normal operation to minimize power consumption.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The continuous operation of the comparison circuit and oscillation circuit is extracted into discrete, event-driven activation periods. Instead of running continuously, these circuits are extracted from the always-on state and activated only during specific events (mode transitions), separating the essential refresh control function from the power-consuming continuous operation.

Inventive Principle:
Principle #2Taking out (Extraction)

3Use of energy by moving object

If the refresh operation is performed in a longer predetermined period at lower temperatures, then power consumption is reduced, but data maintenance capability may be compromised

Engineering Contradiction:
Improvepower consumptionVSAvoiddata maintenance capability
Core Design Contradiction:
Use of energy by moving objectVSReliability

Solution Approach 1:

The refresh period parameter is dynamically changed based on temperature conditions. At lower temperatures where charge leakage is slower, the refresh period is extended to reduce power consumption. At higher temperatures where charge leakage is faster, the refresh period is shortened to maintain data integrity. This parameter adaptation allows the system to optimize between power consumption and data maintenance capability according to actual operating conditions.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The refresh timing system transitions from a static, fixed refresh period to a dynamic, temperature-adjustable refresh period. The system continuously monitors temperature and automatically adjusts the refresh period duration, enabling the memory device to adapt its refresh strategy in real-time based on thermal conditions, thereby maintaining reliability across varying operating environments while optimizing power consumption.

Inventive Principle:
Principle #15Dynamics

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution reduces power consumption by selectively activating the comparison circuit and oscillation circuit only when required, optimizing the refresh period and frequency in response to temperature changes, thereby minimizing overall power usage during self-refresh operations.

Implementation Method 1

The temperature sensor generates a voltage in response to a sensed temperature

Methodology Applied
Scientific EffectTemperature sensing: Thermocouple

Data Source

PatentUS8498167B1Temperature-dependent self-refresh timing circuit for semiconductor memory device
Publication Date: 2013.07.30 ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC
  • US8498167B1 patent drawing
  • US8498167B1 patent drawing
  • US8498167B1 patent drawing

AI summary

A semiconductor memory device with a self-refresh timing circuit is provided. The semiconductor memory device comprises a plurality of memory banks, a command decoder, a bank address generator, a self-refresh counter, and the self-refresh timing circuit. The self-refresh timing circuit comprises a temperature sensor, a reference voltage source, a comparison circuit, an enable circuit, and an oscillation circuit. The comparison circuit compares a voltage from the temperature sensor with a constant voltage from the reference voltage source and generates a comparison signal. The enable circuit activates the comparison circuit when self-refresh operations for at least one refresh row are completed in all memory cell banks. The oscillation circuit generates a self-refresh clock signal which controls the operating frequency of the bank address generator and the self-refresh counter.