Resistive Memory Pulse Polarity for State Determination
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Solution Overview
Problem
Current resistive memory technologies face challenges in accurately determining the state of memory cells during read operations due to the use of pulses with the same width and amplitude, leading to increased complexity in control unit design and manufacturing costs.
Innovation Solution
The proposed solution involves providing a set signal and a reset signal with specific pulse structures, including first and second pulses with opposite polarities, to resistive memory cells based on the logic level of the data, enhancing the accuracy of state determination during read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a set pulse or reset pulse with the same width and amplitude is provided to the memory cell, then the writing operation is simple, but the control unit mistakenly determines the writing state of the memory cell during read operations
Solution Approach 1:
The patent applies parameter changes by differentiating pulse width as a distinguishing parameter between set and reset operations. The first pulse has a first width and the second pulse has a second width different from the first width, allowing the control unit to accurately determine the writing state during read operations while maintaining simple writing operation procedures.
2Measurement precision
If a set pulse or reset pulse with the same amplitude but gradually increased width is provided to the memory cell, then the state determination accuracy is improved, but the complexity of designing the control unit increases and manufacturing cost increases
Solution Approach 1:
The patent uses parameter changes by establishing distinct pulse width values for set and reset operations. The control unit is designed to recognize these different width parameters, enabling accurate state determination without requiring complex gradually increased width sequences, thus reducing control unit design complexity and manufacturing cost.
3Measurement precision
If a set pulse or reset pulse with the same amplitude but gradually increased width is provided to the memory cell, then the state determination accuracy is improved, but the manufacturing cost increases
Solution Approach 1:
The patent applies parameter changes with two distinct pulse widths rather than gradually increased widths. This simplifies the control unit design and reduces manufacturing complexity, thereby lowering manufacturing cost while still enabling accurate state determination during read operations.
Data Source
AI summary
A resistive memory apparatus including a resistive memory cell array and a control unit is provided. The resistive memory cell array includes resistive memory cells. The control unit is configured to receive a logic data, determine a logic level of the logic data, and select one resistive memory cell from the resistive memory cells. The control unit provides a set signal or a reset signal to the selected resistive memory cell in a writing period according to the logic level of the logic data. The set signal includes a first set pulse and a second set pulse having a polarity opposite to that of the first set pulse. The reset signal includes a first reset pulse and a second reset pulse having a polarity opposite to that of the first reset pulse. A writing method of the resistive memory apparatus is also provided.