Memory Interface Using Programmable Delay Units for Clock Domain Synchronization
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Solution Overview
Problem
Existing memory interfaces between different clock domains in computing devices face high latency and resource inefficiencies due to the use of first-in-first-out (FIFO) buffers, which are costly in terms of space and power.
Innovation Solution
A data path interface using programmable delay units (PDUs) and align blocks to synchronize and align data for transmission between a physical layer and a memory device, eliminating the need for FIFO buffers and optimizing data transfer across clock domains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a FIFO buffer is used to bridge data transfer between different clock domains, then data transfer between clock domains is enabled, but latency increases and chip area and power consumption increase
Solution Approach 1:
The patent removes the FIFO buffer from the data path interface between clock domains. Instead of using a buffer that stores and delays data, the invention directly transfers data through a data path interface with alignment logic that synchronizes data without requiring buffering, thereby eliminating the latency and resource consumption associated with FIFO buffers.
Solution Approach 2:
The patent introduces an intermediary alignment logic block that mediates between the two clock domains. This alignment logic uses programmable delay units and control signals to synchronize data timing without requiring a FIFO buffer, enabling direct data transfer while maintaining clock domain synchronization.
2Reliability
If a FIFO buffer is used to bridge data transfer between different clock domains, then data transfer between clock domains is enabled, but chip area and power consumption increase
Solution Approach 1:
The patent removes the FIFO buffer from the data path interface between clock domains. Instead of using a buffer that stores and delays data, the invention directly transfers data through a data path interface with alignment logic that synchronizes data without requiring buffering, thereby eliminating the latency and resource consumption associated with FIFO buffers.
3Reliability
If a FIFO buffer is used to bridge data transfer between different clock domains, then data transfer between clock domains is enabled, but power consumption increases
Solution Approach 1:
The patent removes the FIFO buffer from the data path interface between clock domains. Instead of using a buffer that stores and delays data, the invention directly transfers data through a data path interface with alignment logic that synchronizes data without requiring buffering, thereby eliminating the latency and resource consumption associated with FIFO buffers.
Data Source
AI summary
A data path interface for transferring data to a memory device, comprising: programmable delay units (“PDUs”), wherein data is received by the interface according to a first clock signal and wherein the PDUs apply delays to the received data; and align blocks, wherein the align blocks select certain ones of the delayed data as a function of the first clock signal and a second clock signal, and wherein the selected certain ones of the delayed data are processed for transmission to the memory device according to the second clock signal.