Semiconductor Memory Reference Signal Correction

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Solution Overview

Problem

The semiconductor memory device using ferromagnetic elements as resistance change type memory elements faces challenges in accurately determining the resistance state due to significant wiring parasitic resistance, which limits the miniaturization and arrangement of memory cells, especially with small differences in measured current between high and low resistance states.

Innovation Solution

Incorporating a reference signal correction unit that adjusts the reference signal level based on the selected position of the memory cell within the memory cell array, ensuring equivalent wiring parasitic resistance influence on both the measurement and reference signals, thereby reducing the impact of parasitic resistance and expanding the area where memory cells can be arranged.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If memory cells are miniaturized and arranged in larger numbers, then device capacity and integration density are improved, but wiring parasitic resistance increases and affects measurement accuracy

Engineering Contradiction:
Improvenumber of memory cellsVSAvoidresistance state determination accuracy
Core Design Contradiction:
Quantity of substanceVSMeasurement precision

Solution Approach 1:

A sense amplifier is introduced as an intermediary component between the memory cell array and the read determination circuit. The sense amplifier receives the measurement signal from the memory cell and amplifies it before transmission, thereby compensating for the voltage drop caused by wiring parasitic resistance and maintaining measurement accuracy despite increased wiring length and resistance in miniaturized configurations.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent applies parameter changes by dynamically adjusting the reference signal level based on the selected memory cell position. The read determination circuit modifies the reference signal parameter to account for position-dependent parasitic resistance variations, ensuring accurate resistance state determination across the entire memory cell array regardless of miniaturization-induced wiring changes.

Inventive Principle:
Principle #35Parameter changes

2Area of stationary object

If memory cells are arranged farther from the read determination circuit, then device area utilization is improved, but wiring parasitic resistance increases and current measurement accuracy deteriorates

Engineering Contradiction:
Improvememory cell array coverage areaVSAvoidcurrent measurement accuracy
Core Design Contradiction:
Area of stationary objectVSMeasurement precision

Solution Approach 1:

The sense amplifier serves as a mediator that receives the measurement signal from memory cells located at various distances from the read determination circuit. By amplifying the signal at the point of extraction rather than relying on long-distance transmission, the system maintains current measurement accuracy even when memory cells are arranged across large areas with significant wiring length.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent implements equipotentiality by ensuring that all memory cells, regardless of their distance from the read determination circuit, operate under equivalent electrical conditions through the sense amplifier. The sense amplifier compensates for the cumulative effect of parasitic resistance in the data line and source line, creating an equipotential reference point that enables accurate measurement across the entire array area.

Inventive Principle:
Principle #12Equipotentiality

3Quantity of substance

If wiring length is increased to accommodate more memory cells, then device capacity is improved, but voltage drop due to parasitic resistance increases and signal integrity worsens

Engineering Contradiction:
Improvememory cell countVSAvoidsignal integrity
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The sense amplifier acts as a signal regeneration intermediary positioned between the memory cell array and the read determination circuit. It receives the degraded measurement signal after transmission through long wiring, amplifies it to restore signal levels, and outputs a clean signal to the read determination circuit, thereby maintaining signal integrity despite increased wiring length required for higher memory cell counts.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The sense amplifier performs preliminary amplification of the measurement signal immediately after it is extracted from the memory cell, before the signal traverses the long wiring to the read determination circuit. This preliminary action prevents signal degradation from propagating through the wiring, maintaining voltage levels and signal integrity throughout the extended wiring paths required for high-capacity devices.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach allows for more accurate determination of the resistance state of memory cells, enabling the expansion of the memory cell arrangement region and reducing the limitations imposed by wiring parasitic resistance, thus enhancing the performance and capacity of the semiconductor memory device.

Implementation Method 1

The MRAM includes a ferromagnetic element as a resistance change type memory element, and stores information using a difference in a resistance state of the ferromagnetic element

Methodology Applied
Scientific EffectMagnetoresistance: Magnetoresistance

Implementation Method 2

a resistance value of the selected ferromagnetic element is measured. Then, by determining whether the ferromagnetic element is in a high resistance state or a low resistance state, the stored information can be read

Methodology Applied
Scientific EffectElectrical Resistance: Electrical Resistance

Data Source

PatentUS12148468B2Semiconductor memory device and control device for semiconductor memory device
Publication Date: 2024.11.19 POWER SPIN INC
  • US12148468B2 patent drawing
  • US12148468B2 patent drawing
  • US12148468B2 patent drawing

AI summary

A semiconductor memory device includes a memory cell array including a plurality of memory cells each including a resistance change type memory element configured to store a resistance state and a switch, a read determination circuit that compares a measurement signal from the memory cell selected in the memory cell array with a reference signal to determine a resistance state so as to read information from the resistance change type memory element, and a reference signal correction unit that corrects a level of the reference signal based on a selected position of the memory cell in the memory cell array.