Analog Error Detection in Compute-in-Memory Arrays
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Solution Overview
Problem
Analog compute-in-memory (CiM) architectures face challenges in data reliability due to run-time faults caused by process, voltage, and temperature uncertainty, with existing error correction codes (ECC) being ineffective in detecting errors in analog memory cells, especially in multi-bit representation systems, and conventional ECC solutions being too large, slow, and digitally based, making them unsuitable for CiM architectures.
Innovation Solution
Implementing an in-memory error detection method that counts the total number of 1's in data stored in analog CiM memory cells and stores the summation in binary form using a parallel capacitor structure, with parity bits stored in a C-2C capacitor ladder, allowing for error detection in the analog domain without digitalization, and using summation check logic to compare the summation value with the parity value to detect bit flips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional digital ECC is used in analog CiM architecture, then error detection capability is provided, but device complexity and size increase significantly
Solution Approach 1:
The patent replaces conventional digital ECC mechanisms with an analog-based error detection system. Instead of using complex digital logic circuits to compute syndrome values, the invention uses analog capacitor structures to perform summation operations. The parallel capacitor structure computes the sum of data bits analogously, and the C-2C capacitor ladder generates parity bits through analog charge distribution, eliminating the need for extensive digital ECC hardware.
Solution Approach 2:
The patent changes the operational parameters from digital domain to analog domain. Rather than using binary 0/1 states for error detection, the system uses continuous voltage levels on capacitors to represent and process error information. The analog summation of capacitor charges provides a compact representation of parity information, reducing the physical footprint compared to digital ECC implementations.
2Reliability
If digital-based ECC is implemented, then error correction is provided, but processing speed decreases due to digital conversion requirements
Solution Approach 1:
The patent substitutes digital processing steps with analog operations. The error detection process occurs entirely in the analog domain through capacitor charge summation and voltage comparison, eliminating the time-consuming analog-to-digital conversion required by conventional digital ECC systems. The analog comparator directly compares the computed sum with expected parity values, providing faster error detection.
Solution Approach 2:
The patent performs preliminary analog summation of data bits and generation of parity bits during the normal data storage operation. By pre-computing the analog sum and storing it in the parallel capacitor structure along with the data, the system prepares error detection information in advance, enabling rapid error detection without requiring separate digital processing steps.
3Quantity of substance
If separate memory and processing units are used, then data storage capacity is increased, but data transfer time and power consumption increase
Solution Approach 1:
The patent merges memory storage functionality with error detection computation in a single integrated CiM array. The same array of memory cells that stores data also contains the parallel capacitor structures for error detection, eliminating the need for separate ECC memory modules. This integration allows error detection to occur in-place during data storage, avoiding additional data transfer time.
Solution Approach 2:
The patent makes the memory array multi-functional by embedding both data storage and error detection capabilities within the same physical structure. The memory cells serve dual purposes: storing computational data and simultaneously serving as capacitors for analog error detection. This universal design eliminates the need for dedicated separate memory for ECC information, reducing overall system latency.
4Measurement precision
If multi-bit representation is used in analog CiM, then computational precision is improved, but susceptibility to run-time faults increases
Solution Approach 1:
The patent implements feedback through continuous monitoring of the analog sum and parity bits. The analog comparator provides real-time feedback on data integrity by comparing the computed sum against expected parity values stored in the C-2C capacitor ladder. When discrepancies are detected, the system can trigger error correction or data retransmission, maintaining reliability despite the increased complexity of multi-bit representation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient error detection and mitigation within the CiM architecture, reducing latency and power consumption while providing reliable data storage and processing, especially in neural network applications, by integrating the MAC unit with memory cells and employing analog-based mixed-signal computing.
Implementation Method 1
stores the summation in binary form using a parallel capacitor structure
Implementation Method 2
with parity bits stored in a C-2C capacitor ladder
Data Source
AI summary
Circuitry for a compute-in-memory (CiM) circuit or structure arranged to detect bit errors in a group of memory cells based on a summation of binary 1's included in at least one weight matrix stored to the group of memory cells, a parity value stored to another group of memory cells and a comparison of the summation or the parity value to an expected value.