SRAM Bit Cell Retention Voltage via Self-Service Division
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Solution Overview
Problem
Existing electronic memory circuits face challenges in reducing power leakage during inactive periods while maintaining data integrity, as traditional methods either dissipate energy or occupy significant area with external voltage regulators.
Innovation Solution
A memory array design with two groups of bit cells, where one group is connected to a ground switch and the other to a retention select circuit, allowing the voltage to be reduced by half during inactive periods, thereby reducing leakage current without the need for internal or external voltage regulators.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If voltage regulator is used to provide retention voltage, then data integrity is maintained, but energy is dissipated and area is occupied
Solution Approach 1:
The memory array uses its own bit cells to generate the retention voltage through voltage division, eliminating the need for external voltage regulators. The first group of bit cells receives full supply voltage while the second group receives retained voltage through the retention select circuit, allowing the system to self-produce the required voltage without dissipating energy through regulator components.
Solution Approach 2:
The invention extracts and eliminates the voltage regulator component from the system by using the bit cells themselves to provide the retention voltage function. This removes the harmful element (energy dissipation) while preserving the essential function (maintaining data integrity through voltage reduction).
2Reliability
If voltage regulator is used to provide retention voltage, then data integrity is maintained, but area is occupied
Solution Approach 1:
The memory array uses its own bit cells to generate the retention voltage through voltage division, eliminating the need for external voltage regulators. The first group of bit cells receives full supply voltage while the second group receives retained voltage through the retention select circuit, allowing the system to self-produce the required voltage without dissipating energy through regulator components.
Solution Approach 2:
The invention merges the voltage regulation function with the memory storage function by using bit cells for both purposes. The same bit cells that store data also participate in generating the retention voltage through the voltage division mechanism, eliminating the need for separate voltage regulator hardware.
3Loss of energy
If power is turned off to reduce leakage, then energy consumption is reduced, but data values are lost
Solution Approach 1:
The invention changes the voltage parameter to a lower retention voltage level during inactive periods, allowing the memory array to maintain data integrity while reducing power consumption. The retention select circuit switches the voltage to the first group of bit cells, enabling operation at reduced voltage without complete power shutdown.
Solution Approach 2:
The memory array dynamically adjusts its operating voltage based on activity state. During active periods, full supply voltage is applied; during inactive periods, the retention select circuit switches to provide reduced retention voltage, allowing the system to adapt between performance and power savings modes.
Data Source
AI summary
A memory array that provides an internal retention voltage without a voltage regulator is disclosed. The memory array includes a first group of bit cells coupled between the power supply rail and a ground switch and a second group of bit cells coupled to a retention select circuit. The retention select circuit is coupled to the ground for the first group of bit cells and the power supply rail. The ground switch and the retention select circuit may be operated to switch the bit cells between a nominal operating voltage and a retention voltage. The retention voltage is provided during inactive periods of the memory array to maintain data in the bit cells during the inactive periods.