Clock Locking for Memory Frame Synchronization
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Solution Overview
Problem
Existing memory systems face challenges in achieving high data transfer rates without incurring errors and latency issues, particularly when using multiple data channels, and often require significant power and space for circuits that identify frame boundaries without headers.
Innovation Solution
Implementing a clock locking communications protocol that aligns frames of data with a frame clock, allowing for frame synchronization without headers, and using different clock patterns during active and idle periods to enhance reliability and power efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple data channels are used to increase data transfer rate, then productivity is improved, but reliability deteriorates due to higher error rates
Solution Approach 1:
The patent implements a feedback mechanism where the receiving device detects communication errors on each data channel and sends feedback signals to the transmitting device. The transmitting device uses this feedback to retransmit erroneous data packets, thereby maintaining high reliability even when using multiple data channels for high productivity.
Solution Approach 2:
The patent employs preliminary error detection and correction coding before data transmission across multiple channels. By pre-processing data with error correction codes, the system prepares for potential transmission errors, enabling reliable communication despite the increased error probability from using multiple high-speed channels.
2Productivity
If circuits are added to identify frame boundaries without headers to achieve high data rates, then productivity is improved, but device complexity increases
Solution Approach 1:
The patent uses periodic clock signaling to delimit frames without requiring complex header identification circuits. Regular clock cycles provide natural frame boundaries, allowing the receiving device to synchronize and identify frame starts through simple clock edge detection rather than complex header parsing logic.
Solution Approach 2:
The patent introduces a clock signal as an intermediary that mediates frame boundary identification. Instead of directly analyzing data patterns to find frame starts, the clock signal serves as an intermediate reference that simplifies the synchronization process and reduces the complexity of frame boundary detection circuits.
3Productivity
If complex frame identification circuits are used to achieve high data rates, then productivity is improved, but power consumption increases
Solution Approach 1:
The patent employs periodic clock signals for frame synchronization, which consumes significantly less power than continuous complex signal processing. The periodic nature allows the receiving device to enter low-power states between clock cycles while maintaining synchronization, thereby achieving high data rates with reduced power consumption.
Solution Approach 2:
The clock signal serves a dual purpose: it both drives data transmission and provides frame boundary identification. This self-service approach eliminates the need for separate power-hungry frame identification circuits, as the same clock signal that enables high-speed data transfer also provides the timing reference for frame synchronization.
Data Source
AI summary
Methods, systems, and devices for clock locking for frame-based communications of memory devices are described. A memory system may include a memory device and a host device. The memory device may receive one or more frames of data from the host device, the one or more frames of data communicated by the host device using a first frame clock. The memory device may generate a second frame clock aligned with the one or more frames on receiving the one or more frames and align one or more operations of the memory device with the second frame clock. In some examples, the host device may receive a second set of frames from the memory device based on transmitting the first set of frames. The host device may align one or more operations of the host device with the second set of frames received from the memory device.