Mixed Threshold Voltage SRAM Array for Write Margin
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Solution Overview
Problem
In static random access memory (SRAM) devices, memory cells farther from the input/output (I/O) circuitry experience a larger voltage drop on bit lines, leading to lower write current and difficulty in writing data due to increased resistance, which affects read speed and write margin.
Innovation Solution
The use of strap cells with varying threshold voltages (Vth) for gate transistors, where cells closer to the I/O circuitry have higher Vth for lower current leakage and cells farther away have lower Vth to compensate for voltage drops, improving read speed and write margin without increasing manufacturing constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If memory cells are located farther from the I/O circuitry, then the voltage drop on bit lines increases, but write current decreases and writing becomes difficult
Solution Approach 1:
The patent applies local quality by assigning different threshold voltages to different regions of the memory array. Specifically, memory cells closer to the I/O circuitry use higher threshold voltage transistors to minimize leakage, while memory cells farther away use lower threshold voltage transistors to compensate for voltage drops and maintain adequate write current. This spatial variation in transistor characteristics resolves the contradiction between maximizing array area and maintaining reliable write operations throughout the array.
2Area of stationary object
If memory cells are located farther from the I/O circuitry, then voltage drop increases, but read speed decreases
Solution Approach 1:
The patent uses local quality to address read speed degradation by implementing region-specific threshold voltage optimization. Memory cells in regions experiencing significant voltage drops employ lower threshold voltage transistors that maintain stronger drive currents during read operations, thereby preserving read speed despite the increased distance from I/O circuitry and associated voltage drops.
3Loss of energy
If higher Vth transistors are used for all memory cells, then leakage current is reduced, but write current becomes insufficient for distant cells
Solution Approach 1:
The patent resolves this contradiction by applying local quality through spatially differentiated threshold voltage selection. Cells near the I/O circuitry use higher Vth transistors to minimize leakage current, while cells farther away use lower Vth transistors to ensure sufficient write current reaches them despite voltage drops along the bit lines. This localized optimization allows each region to operate at its optimal performance point.
Data Source
AI summary
A static random access memory (SRAM) device includes a first memory array including a plurality of memory cells, each memory cell including a first pass gate transistor with a first threshold voltage connected to a bit line. The SRAM device further includes a second memory array including a plurality of memory cells, each memory cell including a second pass gate transistor with a second threshold voltage connected to the bit line. The SRAM device further includes a peripheral input-output circuit connected to the bit line. The SRAM device still further includes a column of write current tracking cells, each tracking cell disposed within a row of the first memory array and the second memory array, wherein the first memory array is between the peripheral input-output circuit and the second memory array.