Semiconductor Data Strobe Input Control via Phase Code Synthesis
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Solution Overview
Problem
Semiconductor devices face challenges in efficiently controlling input/output (I/O) operations using data strobe signals, particularly in managing different phases and write operations with and without preamble periods, which affects the stability and speed of data input/output processes.
Innovation Solution
The semiconductor device incorporates a period code generation circuit, code synthesis circuit, and buffer control circuit to generate and manage period codes, synthesis codes, and buffer inactivation signals, allowing for phase control of I/O control signals and stable data strobe signal input based on write operations with or without preamble periods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data strobe signals are used for fast I/O operations with different phases, then operational speed is improved, but control complexity increases
Solution Approach 1:
The patent changes the parameter of signal phase by generating multiple I/O control signals with different phases (e.g., 90-degree phase differences) to enable faster data input/output operations. The period code generation circuit generates control signals with varying phases based on write operation types, allowing the system to optimize speed for different operational modes while managing complexity through structured phase control.
2Stability of the object's composition
If period codes are generated and synthesized to control buffer inactivation, then data strobe signal input stability is improved, but device complexity increases
Solution Approach 1:
The patent segments the control function into distinct modules: a period code generation circuit that creates phase-specific codes, a code synthesis circuit that combines period codes with previous synthesis codes, and a buffer control circuit that uses the synthesized codes to generate buffer inactivation signals. This segmentation stabilizes data strobe signal input by dedicating specific circuits to specific control tasks, while managing overall device complexity through modular functional division.
Solution Approach 2:
The period code generation circuit generates control codes in advance based on the type of write operation (with or without preamble period) before the actual data transfer occurs. This preliminary generation of control signals ensures that the buffer is properly activated or inactivated at the correct timing, stabilizing the data strobe signal input process while avoiding the need for complex real-time decision-making circuits.
3Reliability
If buffer inactivation signals are used to control data strobe signal input, then operational reliability is improved, but manufacturing complexity increases
Solution Approach 1:
The patent introduces an intermediary control mechanism where period codes and synthesis codes act as intermediate signals between the operation type detection and the buffer inactivation control. The code synthesis circuit combines period codes with previous synthesis codes to generate selection control codes, which then control the buffer inactivation signals. This intermediary layer improves operational reliability by ensuring proper timing and sequencing, while the use of standard logic circuits keeps manufacturing complexity manageable.
Data Source
AI summary
A semiconductor device may be provided. The semiconductor device may include a period code generation circuit configured to generate a period code having a logic level combination corresponding to a first command or a second command. The semiconductor device may include a code synthesis circuit configured to add the period code to a previous synthesis code to generate a synthesis code. The semiconductor device may include a buffer control circuit configured to compare the synthesis code with a selection control code to generate a buffer inactivation signal for controlling input of a data strobe signal.