Hybrid PCM and MRAM Chip Architecture for Memory Tradeoffs
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Solution Overview
Problem
Current memory technologies face limitations in combining the advantages of phase change memory (PCM) and magnetoresistive random access memory (MRAM) for optimal data storage, as PCM is best suited for certain conditions while MRAM is best for others, leading to inefficiencies in hybrid memory systems.
Innovation Solution
A chip design integrating a PCM array and an MRAM array over a semiconductor logic circuit, with CMOS circuits controlling both, allowing for data storage using both magnetoresistive and electrical resistive properties, enabling efficient operation and error correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If PCM and MRAM are combined in a hybrid memory system, then data storage efficiency and error correction capabilities are enhanced, but device complexity increases
Solution Approach 1:
The patent combines PCM array and MRAM array into a single hybrid memory device, integrating two different memory technologies to leverage their complementary strengths. The PCM portion provides high-density storage while the MRAM portion provides fast access and non-volatility, creating a unified system that improves overall reliability and error correction capabilities
Solution Approach 2:
The hybrid memory device is segmented into distinct PCM and MRAM portions, each optimized for specific functions. The control circuit selectively accesses different segments based on operational requirements, managing complexity by dividing the system into functional modules that can be independently controlled
2Quantity of substance
If PCM is used for data storage, then high density is achieved, but access speed is limited
Solution Approach 1:
The memory system is divided into PCM and MRAM segments with different performance characteristics. The control circuit intelligently directs read/write operations to the appropriate segment, using MRAM for fast access operations and PCM for high-density storage, thereby resolving the speed-density tradeoff
Solution Approach 2:
The system dynamically selects which memory portion to access based on operational requirements. The control circuit adapts its behavior in real-time, choosing between PCM and MRAM access paths depending on whether speed or density is the priority, making the system flexible rather than static
3Speed
If MRAM is used for data storage, then fast access speed is achieved, but storage density is reduced
Solution Approach 1:
By merging MRAM and PCM in a hybrid architecture, the system achieves both high speed and high density simultaneously. The MRAM portion handles speed-critical operations while the PCM portion provides high-density storage, eliminating the need to choose one over the other
4Adaptability or versatility
If separate control circuits are used for PCM and MRAM, then operational flexibility is improved, but device complexity increases
Solution Approach 1:
The control circuit is designed with multi-functionality to manage both PCM and MRAM portions. Rather than requiring completely separate control logic, the control circuit implements universal control mechanisms that can adapt to different memory types, reducing overall complexity while maintaining operational flexibility
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The hybrid chip effectively leverages the strengths of both PCM and MRAM, enhancing data storage efficiency and error correction capabilities, optimizing performance across different operational conditions.
Implementation Method 1
current may flow across the barrier layer due to quantum tunneling
Implementation Method 2
A difference in resistance between parallel and antiparallel states allows data to be stored
Implementation Method 3
phase change memory (PCM) store data based on a phase of a material
Implementation Method 4
an amorphous, high resistance state may represent a binary '0' and a crystalline, low resistance state may represent a binary '1'
Data Source
AI summary
Apparatuses, systems, and methods are disclosed for a chip with phase change memory (PCM) and magnetoresistive random access memory (MRAM). An apparatus includes a semiconductor circuit formed over a substrate of a chip. An apparatus includes a PCM array formed over a semiconductor circuit. An apparatus includes an MRAM array formed over a semiconductor circuit.


