Masked Write Command Circuit With Delay Paths
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Solution Overview
Problem
Existing memory systems face challenges in implementing error detection and error correction mechanisms due to their sequential operation nature, which complicates the implementation of masked write commands.
Innovation Solution
The implementation of an apparatus and method that includes a memory bank, a local buffer circuit, and an address control circuit with a global buffer circuit, allowing for delayed command processing and separate control signals for read and write operations, enabling non-sequential and simultaneous memory operations to avoid column address conflicts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory operations are performed sequentially as in existing memory systems, then the operation sequence is simple and easy to control, but error detection and correction mechanisms cannot be properly implemented
Solution Approach 1:
The address control circuit is divided into multiple independent command paths (first command path, second command path, etc.), each capable of delaying commands by different amounts. This segmentation allows different memory operations to be processed independently and simultaneously, enabling error detection and correction mechanisms that require non-sequential operation ordering.
Solution Approach 2:
The system dynamically selects different command paths based on the type of memory operation (read or write) and applies different delays to each path. This dynamic adjustment of command timing allows the system to implement masked write commands and error correction mechanisms while maintaining simple sequential control logic at the higher level.
2Reliability
If masked write commands are implemented with delayed command processing, then error detection and correction are enabled, but column address conflicts may occur between simultaneous operations
Solution Approach 1:
The address control circuit preliminarily determines the delay amount for each command path before executing the masked write operation. By pre-calculating and applying the correct delays based on command types, the system ensures that read and write operations are timing-aligned properly, preventing column address conflicts before they can occur.
Solution Approach 2:
The address control circuit acts as an intermediary between the command input and the memory banks, introducing controlled delays through multiple command paths. This intermediary function coordinates the timing of simultaneous read and write operations, allowing them to proceed without column address conflicts while enabling error detection and correction mechanisms.
3Adaptability or versatility
If separate control signals are used for read and write operations, then independent operation control is achieved, but the control circuit complexity increases
Solution Approach 1:
The control signal generation is segmented into separate functions for read and write operations. The address control circuit generates different control signals (first control signals for reads, second control signals for writes) through distinct command paths, enabling independent control of each operation type while using a modular approach that limits overall complexity.
Data Source
AI summary
Apparatuses and methods for implementing masked write commands are disclosed herein. An example apparatus may include a memory bank, a local buffer circuit, and an address control circuit. The local buffer circuit may be associated with the memory bank. The address control circuit may be coupled to the memory bank and configured to receive a command and an address associated with the command. The address control circuit may include a global buffer circuit configured to store the address. The address control circuit may further be configured to delay the command using one of a plurality of command paths based, at least in part, on a write latency and to provide the address stored in the global buffer circuit to the local buffer circuit to be stored therein.