Level-Shifting Pulse Latch for Dual-Power Memory Clock
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Solution Overview
Problem
Conventional level-shifting pulse latches experience excessive power loss due to the need to level-shift between system and memory power supply voltages, especially when the system power supply voltage is higher than the memory power supply voltage, leading to inefficiencies in scenarios with varying power domains.
Innovation Solution
A level-shifting pulse latch design that includes a level-shifting inverter, a pass transistor, and a memory-power-domain latch, which inverts and level-shifts the system clock signal, and uses internal clock signals to control the latch, preventing unnecessary power discharge and maintaining the self-timed memory clock signal independently of the system clock reset.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional level-shifting pulse latch is used to transfer clock signal between power domains, then power domain isolation is achieved, but excessive power loss occurs due to DC current discharge
Solution Approach 1:
The latch circuit dynamically adjusts its transparency state based on clock signal edges. The latch is transparent only during specific clock phases (rising or falling edge depending on mode) and opaque during others, allowing dynamic control of signal transfer and power consumption. This is achieved through clock signal control of the latch transparency, enabling the circuit to switch between transparent and opaque states to minimize unnecessary power discharge while maintaining reliable level-shifting operation.
Solution Approach 2:
The latch circuit operates in periodic cycles synchronized with the clock signal, alternating between transparent and opaque states. This periodic operation allows the circuit to transfer signals only during appropriate clock phases while remaining isolated during other phases, thereby reducing continuous DC current discharge. The periodic transparency control aligns with clock edges to achieve both power savings and reliable level-shifting.
2Device complexity
If system clock reset is tied to memory clock reset in conventional design, then synchronization is simplified, but memory clock assertion cannot be maintained independently when system clock resets
Solution Approach 1:
The clock synchronization function is segmented into two independent components: system clock domain handling and memory clock domain handling. The latch circuit accepts system clock input but generates memory clock output independently, allowing each domain to operate autonomously. This segmentation enables the memory clock to maintain its assertion state independently of system clock resets, while still achieving proper synchronization through the latch's edge-triggered operation.
Solution Approach 2:
The latch circuit acts as an intermediary between the system clock domain and memory clock domain. It receives the system clock signal and memory select signal as inputs, processes them through the latch mechanism, and generates the memory clock output. This intermediary function allows independent control of memory clock assertion while maintaining synchronization, as the latch mediates the relationship between the two clock domains without tying their reset operations directly together.
3Adaptability or versatility
If level-shifting inverter is used to invert clock signal from system power domain to memory power domain, then voltage level adaptation is achieved, but power consumption increases due to voltage differential
Solution Approach 1:
The circuit changes its operational parameters based on the power domain configuration. The latch circuit is designed to operate with different voltage levels at its inputs and outputs, adapting to the specific system and memory power domain voltages. By controlling the latch transparency during specific clock phases, the circuit minimizes the time during which voltage differential exists across the level-shifting path, thereby reducing power consumption while maintaining voltage level adaptation capability.
Data Source
AI summary
A level-shifting pulse latch is provided for a self-timed memory clock signal for a memory. The level-shifting pulse latch includes a system-power-domain-to-memory-power-domain level-shifter that inverts and level-shifts a system clock signal into an inverted version of the system clock signal. A pass transistor controls whether the inverted version of the system clock signal drives a memory-power-domain latch to produce the self-timed memory clock signal.