Memory Test Device BIST Hardware Failure Detection
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Solution Overview
Problem
Existing memory devices, particularly MRAM and other non-volatile random-access memory types, face hardware failure due to endurance and reliability issues, with damaged memory cells causing faults that current detection mechanisms fail to address effectively.
Innovation Solution
A built-in self-test (BIST) apparatus is implemented within the memory array, comprising a controller and pattern generator that performs twice memory test operations using background and pattern data to detect hardware failures in memory sub-arrays, and includes mechanisms for repairing damaged cells based on the type of memory used.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If memory cells are written or programmed repeatedly to increase storage capacity and accessibility, then the utility and versatility of the memory device is improved, but the hardware reliability deteriorates due to endurance limitations and cell damage
Solution Approach 1:
The patent implements preliminary damage detection through built-in test circuits that continuously monitor memory cell health before failures occur. The system performs read operations and compares retrieved data with expected values to identify damaged cells early, enabling preventive measures to be taken before the damage propagates and causes system failures.
Solution Approach 2:
The patent establishes a feedback mechanism where test results from memory cell readings are fed back to the control logic. When damaged cells are detected, the system generates error signals that trigger repair operations or data recovery procedures, creating a closed-loop system that continuously maintains memory reliability despite repeated write operations.
2Reliability
If hardware failure detection mechanisms are added to memory devices, then the reliability and detectability of failures is improved, but the device complexity increases
Solution Approach 1:
The patent merges the test circuits with the existing memory array structure, using shared read paths and control logic. The built-in self-test (BIST) functionality is integrated into the memory controller, allowing failure detection capabilities to be added without requiring completely separate testing hardware, thus minimizing the increase in device complexity.
Solution Approach 2:
The patent designs the test circuits to perform multiple functions: normal memory read operations, failure detection, and repair coordination. The same read paths and control logic used for regular memory operations are also utilized for testing, making the detection mechanism multi-functional and reducing overall system complexity despite adding failure detection capabilities.
3Measurement precision
If twice memory test operations are performed to ensure accurate hardware failure detection, then the measurement precision is improved, but the loss of time increases due to additional testing steps
Solution Approach 1:
The patent implements periodic testing where the first test operation checks for hardware failures and the second test operation verifies repair effectiveness or performs additional verification. These tests are conducted at strategically chosen intervals rather than continuously, balancing the need for accurate detection with the time cost of testing. The periodic nature allows the system to maintain precision while minimizing time loss by testing only when necessary.
Data Source
AI summary
A testing device for memory includes a memory array and a test apparatus. The test apparatus includes a controller and a pattern generator. The pattern generator generates a background data, a first pattern data, and a second pattern data. The controller sets up the background data to a to-be-tested memory sub-array of the memory sub-arrays, performs a first memory test operation with the to-be-tested memory sub-array according to the first pattern data for detecting an occurrence of a hardware failure of the to-be-tested memory sub-array is occurred during the first memory test operation. The controller performs a second memory test operation with the to-be-tested memory sub-array according to the second pattern data for detecting the occurrence of the hardware failure of the to-be-tested memory sub-array during the second memory test operation in response to the hardware failure of the to-be-tested memory sub-array is not occurred during the first memory test operation.