Memory Management Device Arbiter Load Reduction
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Solution Overview
Problem
Conventional memory management systems face increased load on the arbiter due to the sequential nature of refresh and calibration processes in storage devices, leading to higher costs and inefficiencies as the number of process requests grows.
Innovation Solution
A memory management device that includes detecting units for timing synchronization and a command generating unit to create common commands and sideband signals for overlapping processes, allowing for prioritization and efficient arbitration, thereby reducing the arbiter's load.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate commands are issued for each process (memory access, refresh, calibration), then each process can be independently controlled, but the number of arbitrations increases and the load on the arbiter increases
Solution Approach 1:
The patent combines multiple process requests (memory access, refresh, calibration) into a single bundled command. The host device issues one command that includes process identification information and timing information, allowing the storage device to internally distinguish and execute different processes without requiring separate arbitrations for each process type. This merging approach maintains independent process control while significantly reducing the number of arbitration events.
Solution Approach 2:
The patent creates a universal command structure that can represent multiple different processes within a single command format. The bundled command includes process identification information that allows the storage device to determine whether the command refers to memory access, refresh, calibration, or other processes. This multi-functional command reduces arbiter load while preserving the ability to control each process type independently through the process identification field.
2Reliability
If refresh and calibration processes are performed sequentially with traditional arbitration, then each process receives dedicated resource allocation, but the total process time increases and system productivity decreases
Solution Approach 1:
The patent implements preliminary action by allowing the host device to issue bundled commands that include timing information indicating when each process should be executed. The storage device uses this advance timing information to schedule and execute multiple processes (refresh, calibration, memory access) in an optimized sequence without requiring sequential arbitration. This ensures each process receives appropriate resource allocation while significantly reducing total execution time and improving system throughput.
3Quantity of substance
If the number of host devices increases, then system capacity and processing capability increase, but the number of process requests increases and the arbiter becomes a bottleneck
Solution Approach 1:
The patent enables multiple host devices to issue bundled commands that consolidate multiple process requests into fewer transmission events. Each bundled command contains process identification information that allows the storage device to internally manage multiple processes without requiring proportional increases in arbitration capacity. This approach allows system capacity to scale with the number of host devices while the arbiter load increases much more slowly.
Data Source
AI summary
The load on an arbiter that conducts arbitration among host devices is reduced in an information processing system that includes the host devices and a storage device. A memory management device includes detecting units and a command generating unit. Each of the detecting units detects a timing to execute a predetermined process for the storage device. The command generating unit generates a command common to the predetermined processes subjected to the detection in the detecting units, and a sideband signal unique to each of the predetermined signals having the execution timings detected.